Oblique Deposition Etching Barrier for Vertical Transistor One-Side Contact
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Solution Overview
Problem
As semiconductor devices integrate more transistors within a limited substrate area, the challenge lies in effectively forming one side contacts for vertical transistors while minimizing parasitic capacitance between bit lines, which is difficult due to the reduced substrate surface area and the need for precise etching barriers.
Innovation Solution
A method involving the formation of wall bodies on a semiconductor substrate, where an etching barrier is created using oblique directional deposition, leveraging a shadow effect to selectively expose one sidewall for bit line contact, and subsequent steps to form a bit line contacting the exposed active region, including the use of liners, sacrificial layers, and plasma-enhanced chemical vapor deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical transistors are integrated to increase integration density, then the number of transistors per unit area increases, but the substrate surface area available for bit line routing is reduced
Solution Approach 1:
The patent transitions from planar bit line routing to three-dimensional sidewall routing. By forming bit lines along the sidewalls of active pillars rather than on the substrate surface, the invention utilizes the vertical dimension and lateral sidewall space, thereby increasing integration density without consuming additional substrate surface area.
2Manufacturing precision
If oblique directional deposition is used to form etching barrier, then selective coverage of trench bottom edges is achieved through shadow effect, but the deposition process complexity increases
Solution Approach 1:
The patent employs the shadow effect during oblique directional deposition to enable the structure itself to define the deposition pattern. The protruding wall bodies automatically create shadow regions that prevent deposition material from reaching certain trench bottom edges, while other edges remain exposed. This self-defining mechanism achieves selective coverage without requiring additional photolithography patterning steps or complex mask alignment procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration of vertical transistors with reduced parasitic capacitance by selectively exposing the active region for bit line contact, enhancing integration density and reducing substrate surface occupation.
Implementation Method 1
forming an etching barrier by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein one of two bottom edge portions of the trench is selectively exposed by a shadow effect which partially covers the deposition due to upper portions of the wall bodies
Implementation Method 2
The etching barrier may be formed by sputtering deposition
Implementation Method 3
The etching barrier may be formed by plasma-enhanced chemical vapor deposition (PECVD)
Data Source
AI summary
A method for fabricating an etching barrier includes forming wall bodies with a trench in between the wall bodies in a semiconductor substrate. An etching barrier is formed by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein one of two bottom edge portions of the trench is not covered by the deposition due to a shadow effect by upper portions of the wall bodies.