Oblique Die Stacking in BGA Memory Packages
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Solution Overview
Problem
The challenge in microelectronic packaging is to create compact multi-chip memory packages that efficiently interconnect numerous chips with a large number of input and output connections without increasing the package size, which is essential for portable devices and data servers to enhance bandwidth and reduce power consumption.
Innovation Solution
The solution involves a microelectronic package configuration where semiconductor chips are stacked with edges oriented at oblique angles relative to the substrate's peripheral edges, allowing for a standardized common interface on a circuit panel, enabling efficient interconnection of terminals and reducing the variation in electrical lead lengths between contacts and terminals, thereby optimizing signal transmission speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple chips are interconnected with numerous I/O connections, then bandwidth and functionality are improved, but package size increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of chips to a three-dimensional stacked configuration. Multiple memory chips are vertically stacked above a substrate, allowing numerous I/O connections to be achieved through vertical stacking rather than horizontal spreading. This dimensional change enables high bandwidth connectivity while maintaining a compact footprint, directly resolving the contradiction between increased bandwidth requirements and package size constraints.
2Area of stationary object
If chips are arranged to minimize package size, then area is reduced, but variation in electrical lead lengths increases
Solution Approach 1:
The patent employs asymmetric orientation of chips within the stacked configuration. Chips are rotated at specific angles (e.g., 45 degrees) relative to each other and to the substrate edges, creating an asymmetric arrangement. This asymmetric positioning, combined with strategically placed buffer contacts at corners, compensates for variations in electrical lead lengths by providing equal-length signal paths through geometric symmetry breaking, thereby maintaining manufacturing precision while achieving compact packaging.
3Adaptability or versatility
If standard common interface is implemented on circuit panel, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal common interface design where the substrate provides standardized terminal arrays that can interface with different types of circuit panels and systems. The substrate acts as a universal platform that accommodates multiple chip configurations and orientations while presenting a standardized interface to the external world. This multi-functional design enables the same package structure to be used across different applications and systems, improving adaptability without proportionally increasing complexity.
Data Source
AI summary
A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate.