Oblique IC Cell Layout for Better Pin Access and Fewer M0 Tracks
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Solution Overview
Problem
Existing IC design approaches face challenges in efficiently routing and placing semiconductor devices due to constraints on spacing and interactions between adjacent cells, leading to increased power consumption and area usage.
Innovation Solution
The proposed solution involves designing cells with oblique IO patterns and boundaries, allowing for easier access and connection without increasing the number of M0 tracks, thus improving power and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional rectangular cell boundaries and IO patterns are used, then routing connectivity is achieved, but the number of M0 tracks increases and power consumption rises
Solution Approach 1:
The patent applies asymmetry by replacing traditional rectangular cell boundaries with oblique (slanted) boundaries, and by orienting IO patterns at oblique angles rather than aligned with cardinal directions. This asymmetric geometry optimizes the routing path efficiency, allowing signals to access pins with fewer M0 track crossings, thereby reducing power consumption while maintaining connectivity.
Solution Approach 2:
The patent introduces oblique dimensions by tilting cell boundaries and IO patterns at specific angles (e.g., 45 degrees) relative to the standard grid. This dimensional transformation creates more efficient routing angles that reduce the number of horizontal M0 track crossings needed for signal propagation, thus lowering power consumption without compromising device functionality.
2Area of stationary object
If traditional rectangular cell boundaries are used, then manufacturing simplicity is maintained, but pin access efficiency decreases and area usage increases
Solution Approach 1:
The patent employs asymmetric oblique boundaries that slant at specific angles to optimize pin accessibility. This asymmetric design allows IO patterns to be accessed more directly from adjacent cells, reducing the overall chip area required for equivalent functionality, while the oblique angles are chosen to be manufacturable with standard fabrication processes.
Solution Approach 2:
The patent changes the geometric parameters of cell boundaries from 0-degree (rectangular) to oblique angles (e.g., 45 degrees). This parameter transformation improves pin access efficiency and area utilization while remaining within the capabilities of existing manufacturing technologies, as the oblique angles can be implemented through standard photolithography and etching processes.
3Productivity
If oblique IO patterns are implemented, then pin access efficiency improves and M0 track usage reduces, but design complexity increases
Solution Approach 1:
The patent segments the chip into cells with standardized oblique boundaries and IO pattern orientations. By establishing a consistent segmentation scheme across the entire design, the initial increase in design complexity is amortized, and reuse of standardized oblique cell templates simplifies the overall layout process while maintaining high pin access efficiency.
Solution Approach 2:
The patent creates universal oblique cell templates that can be reused throughout the design. These standardized oblique cells with fixed boundary angles and IO pattern orientations serve multiple functions: they provide efficient pin access, reduce M0 track usage, and can be instantiated repeatedly across different parts of the chip, thereby reducing overall design complexity through reuse.
Data Source
AI summary
An integrated circuit (IC) device includes a substrate, at least one active region over the substrate and elongated along a first axis, at least one gate region extending across the at least one active region, and at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to other circuitry. The at least one IO pattern extends obliquely to the at least one active region or the at least one gate region.