Semiconductor Chip Module Oblique Redistribution Lines

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Solution Overview

Problem

Semiconductor devices face reliability issues due to electrostatic discharge (ESD) phenomena, particularly the charged device model (CDM), which can cause permanent damage through charge accumulation and discharge, degrading the device's CDM property.

Innovation Solution

A semiconductor chip module and package design featuring first and second semiconductor chips adjacent with a scribe line region, utilizing redistribution lines and pads that are obliquely formed to minimize overlap with signal lines, thereby reducing charge accumulation and improving CDM properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If redistribution lines are formed parallel to signal lines to simplify manufacturing, then manufacturing precision is improved, but charge accumulation increases causing CDM property degradation

Engineering Contradiction:
Improvealignment precisionVSAvoidCDM property
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The redistribution lines are intentionally formed at an oblique angle (e.g., 45 degrees) relative to the signal lines rather than being parallel, creating an asymmetric arrangement that reduces overlapping area and minimizes charge accumulation during ESD events

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

Instead of only varying the lateral position of redistribution lines (one-dimensional adjustment), the patent introduces angular orientation as an additional degree of freedom (two-dimensional adjustment), allowing the lines to extend in different directions to minimize overlap with signal lines

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the number of redistribution lines is increased to improve electrical coupling, then electrical conductivity is improved, but the overlapping area with signal lines increases causing more charge accumulation

Engineering Contradiction:
Improveelectrical couplingVSAvoidcharge accumulation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

By orienting redistribution lines at oblique angles, the patent enables denser routing of multiple lines without increasing overlap with signal lines, as the angular separation creates more available space in the lateral dimension

Inventive Principle:
Principle #4Asymmetry

3Reliability

If redistribution lines extend directly beneath signal lines to maximize electrical coupling, then electrical conductivity is improved, but charge accumulation increases during ESD events

Engineering Contradiction:
Improveelectrical couplingVSAvoidelectrostatic discharge damage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The oblique orientation creates an asymmetric spatial relationship where redistribution lines are deliberately positioned to avoid being directly beneath signal lines, reducing the overlapping area that would otherwise act as a charge accumulation zone during ESD events

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS10460771B2Semiconductor chip module and semiconductor package including the same
Publication Date: 2019.10.29 SK HYNIX INC
  • US10460771B2 patent drawing
  • US10460771B2 patent drawing
  • US10460771B2 patent drawing

AI summary

A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines. The redistribution pads includes shared redistribution pads electrically coupled in common to the redistribution lines electrically coupled to the bonding pads of the first semiconductor chip and the redistribution lines electrically coupled to the bonding pads of the second semiconductor chip; and individual redistribution pads individually electrically coupled to the redistribution lines which are not electrically coupled with the shared redistribution pads.