Oblique Interconnect Architecture for Lower-Latency SoC Core Routing
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Solution Overview
Problem
Conventional microelectronic packaging architectures face limitations in connecting multiple processor cores efficiently due to increased latency and resistive-capacitive delays as the number of cores grows, with conventional network topologies restricted to orthogonal routes, leading to suboptimal performance in high-performance computing systems.
Innovation Solution
A microelectronic assembly featuring a semiconductor wafer with a grid of network nodes connected via local adjacent orthogonal connections and oblique connections on a low-loss dielectric interconnection structure, allowing direct bonding to enhance electrical connectivity between nodes, reducing latency and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional orthogonal Manhattan routing is used to connect processor cores, then the routing structure is simple and easy to manufacture, but the connection length increases and latency increases as the number of cores increases
Solution Approach 1:
The patent introduces oblique routing paths at 45-degree angles between processor cores, adding a diagonal dimension to the traditional orthogonal routing grid. This allows signals to traverse shorter distances by cutting across the grid rather than following orthogonal paths, reducing connection latency while maintaining manufacturing feasibility through standardized lithographic patterns.
Solution Approach 2:
The patent employs curved routing paths that arc between processor cores instead of strict orthogonal or linear oblique paths. These curved routes optimize the geometric efficiency of signal propagation, minimizing connection length while avoiding the manufacturing complexity of arbitrary curves by using controlled arc segments that can be implemented with standard fabrication processes.
2Productivity
If the number of processing cores is increased to improve computing performance, then processing capacity increases, but resistive-capacitive delay of metal wiring increases and performance gains diminish
Solution Approach 1:
The patent applies different routing strategies to different regions of the processor array. Local oblique and curved routing paths are implemented in regions where they provide the most benefit, while maintaining simpler orthogonal routing where sufficient. This localized optimization reduces overall resistive-capacitive delay without requiring complete redesign of the entire routing infrastructure, enabling scalable performance improvement.
Solution Approach 2:
By introducing oblique and curved routing dimensions, the patent creates shorter electrical paths between distant cores, reducing the resistive-capacitive delay that scales with conventional orthogonal routing. This dimensional enhancement allows high-core-count designs to maintain lower signal delays, preserving performance scalability.
3Loss of time
If hierarchical mesh network topology is used to improve latency within network, then latency between neighboring nodes improves, but connections are still limited to neighboring nodes and cannot propagate efficiently across several nodes
Solution Approach 1:
The patent extends the hierarchical mesh by superimposing oblique routing layers that cut across traditional mesh boundaries. This allows signals to propagate more efficiently across multiple nodes by utilizing diagonal paths that span several logical hops in fewer physical steps, enhancing both local and long-distance connection efficiency within the network topology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables shorter connection lengths and reduced latency, improving the performance of multi-core processor systems by allowing oblique routing, which decreases connection lengths by up to 29.3% compared to conventional designs, thereby enhancing the scalability and efficiency of high-performance computing systems.
Implementation Method 1
the resistive-capacitive delay of metal wiring may increase as the number of cores increases
Implementation Method 2
an interconnection structure comprising a low-loss dielectric material
Implementation Method 3
The semiconductor wafer may be directly bonded to the interconnection structure using direct dielectric bonding
Implementation Method 4
thermocompression bonding, or other techniques
Data Source
AI summary
A microelectronic assembly may include a semiconductor wafer having first and second surfaces extending in first and second directions, the semiconductor wafer having network nodes connected to one another via local adjacent connections each extending in only one of the first and second directions, and an interconnection structure comprising a low-loss dielectric material and having first and second opposite surfaces extending in third and fourth directions each oriented at an oblique angle relative to the first and second directions, the interconnection structure having local oblique connections each extending in only one of the third and fourth directions. The semiconductor wafer may be directly bonded to the interconnection structure such that each of the network nodes is connected with at least one of the other network nodes, without use of conductive bonding material, through at least one of the local adjacent connections and at least one of the local oblique connections.