3D Electronic Module Oblique Wiring for Signal Integrity
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Solution Overview
Problem
Current methods for interconnecting stacked chips, such as Chip on Chip (CoC) technology, are costly and result in a larger horizontal footprint and signal integrity issues, especially at high frequencies beyond 2 GHz, due to electron reflections at right-angle connections.
Innovation Solution
A 3D electronic module design that combines CoC and Wire Direct Over Die (WDoD) technologies, where chips are stacked with oblique wiring connections to vertical buses within an epoxy resin molding, ensuring consistent conductor lengths and minimizing horizontal surface area, while avoiding electron reflections by using non-straight wiring to compensate for vertical bus length differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Chip on Chip (CoC) technology with horizontal wiring is used, then manufacturing cost is reduced, but horizontal footprint area increases significantly
Solution Approach 1:
The patent transitions from horizontal wiring (2D plane) to vertical wiring (3D space) by implementing wire bonds that extend vertically from chip pads to bonding pads on the substrate. This dimensional change allows electrical connections to be made in the vertical direction, dramatically reducing the horizontal footprint area while maintaining manufacturing feasibility through established wire bonding processes
2Area of stationary object
If vertical wiring with right-angle connections is used, then horizontal footprint area is reduced, but signal integrity deteriorates due to electron reflections
Solution Approach 1:
The patent replaces symmetric right-angle connections with asymmetric oblique connections. The wire bonds are routed at angles between 45 and 135 degrees relative to the vertical direction, creating asymmetric connection paths that eliminate the perpendicular intersections causing electron reflections. This asymmetric routing maintains the compact vertical footprint while preserving signal integrity by avoiding harmful reflection points
3Device complexity
If wiring length is not compensated, then manufacturing complexity is reduced, but signal integrity varies across different chips in the stack
Solution Approach 1:
The patent systematically adjusts the wiring length parameter to compensate for variations in vertical bus lengths across different chip positions in the stack. By calculating and implementing specific length adjustments for each chip's wire bonds, the total electrical path length from any chip pad to the interconnection circuit is equalized. This parameter optimization ensures consistent signal characteristics and impedance matching across all chips without requiring complex manufacturing processes
Data Source
Figure 1~2b
Figure 3~4
Figure 5a~5b
AI summary
The invention relates to a 3D electronic module comprising, along a so-called vertical direction, a stack (4) of electronic slices (16), each slice comprising at least one chip (1) furnished with interconnection pads (10), this stack being assembled to an interconnection circuit (2) of the module furnished with connection balls, the pads (10) of each chip being connected by electrical wiring leads (15) to vertical buses (41) that are in turn electrically linked to the module interconnection circuit (2), a wiring lead and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnection circuit, characterized in that each electrical wiring lead (15) is linked to its vertical bus (41) while forming an oblique angle (α2) in a vertical plane and in that the length of the wiring lead between a pad of a chip of one slice and the corresponding vertical bus is different from the length of the wiring lead between the same pad of a chip of another slice and the corresponding vertical bus, obtained by a non-rectilinear wiring of the wiring lead so as to compensate for the difference in vertical length of the vertical bus from slice to slice, in such a way that the electrical conductor between the pad of a chip of a slice and the interconnection circuit, and the electrical conductor between the same pad of a chip of the other slice and the interconnection circuit, have the same length.