Observability-Based Clock Gating for IC Power Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Designing integrated circuits to minimize power consumption is challenging due to the need to determine when logic elements can be disabled without impacting functionality, often requiring additional logic that may negate power savings.
Innovation Solution
An integrated circuit design system that identifies observability-based clock gating conditions, allowing for the disabling of secondary logic elements when their output is not a function of a first input, thereby reducing power consumption without affecting functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If additional logic is added to determine when logic elements can be disabled, then power consumption control improves, but device complexity increases
Solution Approach 1:
The system uses the existing logic elements and their natural signal flows to determine disabling conditions, rather than adding separate control logic. The observability-based clock gating conditions are derived from the functional relationships already present in the circuit, allowing the circuit to self-determine when disabling is appropriate without external control overhead.
Solution Approach 2:
The system pre-computes and stores observability-based clock gating conditions during the design phase, so that during operation, the logic elements can be disabled immediately when conditions are met without requiring complex real-time analysis. This preliminary preparation eliminates the need for additional runtime control logic.
2Use of energy by moving object
If logic elements are disabled to save power, then power consumption decreases, but functionality may be compromised
Solution Approach 1:
The system uses feedback from the output signals and logic relationships to determine when disabling a logic element will not affect functionality. By monitoring whether the output of a logic element is actually used in the current operational context, the system ensures that disabling occurs only when safe, maintaining reliability while achieving power savings.
Solution Approach 2:
The system applies disabling selectively to specific logic elements based on their individual observability conditions, rather than applying a global disable signal. This localized approach ensures that each logic element is disabled only when its specific output is not needed, preserving overall circuit functionality while maximizing power savings at the component level.
3Use of energy by moving object
If observability-based conditions are used to disable logic elements, then power savings are achieved, but detection and measurement difficulty increases
Solution Approach 1:
The system creates simplified representations (copies) of the observability conditions during design analysis, storing them in a format that can be easily evaluated during operation. Instead of performing complex real-time analysis of signal flows, the pre-computed condition models allow for simple comparison and immediate decision-making about logic element disabling.
Data Source
AI summary
An integrated circuit design system, method, and computer program product are provided that takes into account observability based clock gating conditions. In use, at least one condition is identified where an output of a first logic element is not a function of a first input of the first logic element, due to a second input of the first logic element. To this end, at least one second logic element may be disabled based on the identified condition for power savings or other purposes.