Obstacle-Avoiding Signal Bus Routing in IC Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complex task of routing signal buses in integrated circuit designs, especially wide buses, is challenging due to numerous obstacles and requires manual trial-and-error methods, often resulting in sub-optimal solutions with inefficient use of IC real-estate and difficulty in maintaining regularity and avoiding path blockages.
Innovation Solution
A computer-implemented bus routing tool generates escape nodes to construct a three-dimensional routing solution graph, dynamically determining node locations to avoid obstacles and ensure regularity, allowing for automated obstacle-avoidance routing and optimal path determination from source to target locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual trial-and-error routing is used, then routing constraints such as signal timing and delay can be satisfied, but routing time is excessive and IC real-estate utilization is sub-optimal
Solution Approach 1:
The routing system performs self-service by automatically evaluating multiple candidate routing solutions against timing and delay constraints without requiring manual iteration. The system generates, evaluates, and selects optimal routing paths autonomously, eliminating the time-consuming manual trial-and-error process while maintaining constraint satisfaction.
Solution Approach 2:
The patent replaces the mechanical manual routing process with an automated computer-implemented system. The routing evaluation logic systematically assesses candidate solutions using algorithms that calculate signal timing and delay, substituting human manual manipulation with automated computational analysis to achieve both speed and accuracy.
2Ease of manufacture
If manual routing is performed, then routing solutions can be obtained, but IC real-estate is wasted and subsequent bus routing is hindered
Solution Approach 1:
The system performs preliminary action by evaluating the impact of routing decisions on future bus routing before finalizing the current route. The routing evaluation logic considers long-term IC real-estate utilization by predicting how current routing choices affect subsequent routing operations, enabling optimal space management from the outset.
Solution Approach 2:
The patent implements feedback mechanisms where the routing evaluation logic continuously monitors IC real-estate utilization and adjusts routing decisions accordingly. The system uses feedback from congestion analysis and space utilization metrics to optimize routing paths, ensuring efficient use of available IC real-estate while maintaining routing feasibility.
3Productivity
If automated routing is implemented, then routing efficiency is improved, but maintaining routing regularity and avoiding path blockages becomes challenging
Solution Approach 1:
The system generates multiple disposable candidate routing solutions that are evaluated and discarded in favor of the optimal solution. This approach allows the automated system to explore various paths without committing to sub-optimal regularity early, ultimately selecting the best route that satisfies both efficiency and regularity requirements.
Solution Approach 2:
The routing evaluation logic dynamically changes evaluation parameters to balance routing efficiency with regularity maintenance. The system adjusts weighting factors for different routing criteria based on the specific design context, enabling the automated process to achieve both high productivity and manufacturing precision by adapting evaluation parameters to situational requirements.
Data Source
AI summary
Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location can be determined.