On-Chip Clock Controller Pulse Debugging for IC Test
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Solution Overview
Problem
Current test devices face challenges in verifying the correctness of high-frequency clock waveforms and debugging issues during at-speed tests of integrated circuits, leading to increased verification time and cost due to difficulties in isolating on-chip PLL failures and verifying clock pulse correctness.
Innovation Solution
The proposed test device includes an on-chip-clock controller, pulse debugging circuit, and register circuit to generate and verify the correctness of output clocks, allowing for the determination of abnormal test statuses and reducing the complexity of debugging by storing and outputting pulse records using a reliable clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an on-chip PLL and OCC are used to generate high-frequency clock for at-speed test, then the test can be performed with low-cost ATE, but it becomes difficult to verify clock waveform correctness and debug test failures
Solution Approach 1:
The patent introduces an intermediary verification mechanism between the OCC and the CUT. A verification circuit captures the output clock signal from the OCC and compares it against expected timing characteristics. This intermediary layer allows the test system to indirectly verify clock correctness without requiring external high-frequency measurement equipment, thus resolving the contradiction between using low-cost ATE and maintaining debug capability.
Solution Approach 2:
The patent implements feedback by capturing the actual clock signal generated by the OCC during test operation and using this captured signal to verify timing correctness. The verification circuit provides feedback information about whether the clock meets specifications, enabling debuggers to identify timing-related test failures and distinguish them from CUT functional errors.
2Productivity
If the on-chip PLL is used as clock source, then at-speed test can be performed, but signal isolation is insufficient causing test patterns to change PLL settings and produce incorrect clock frequencies
Solution Approach 1:
The patent applies preliminary action by capturing and verifying the clock signal characteristics before they are used to drive the CUT. The verification circuit checks the clock frequency and timing parameters in advance, ensuring that the PLL is operating at the correct frequency before the actual at-speed test begins. This prevents test patterns from causing frequency drift undetected during test execution.
Solution Approach 2:
The verification mechanism provides continuous feedback about PLL output correctness. If the captured clock signal deviates from expected parameters, the system can detect this before it affects test results, allowing for real-time correction or test abort to maintain frequency accuracy throughout the test process.
3Measurement precision
If clock verification is performed externally, then waveform correctness can be confirmed, but high-frequency clock verification capability is lacking in low-cost ATE
Solution Approach 1:
The patent extracts the clock verification function from external test equipment and relocates it to the chip itself. By implementing the verification circuit within the CUT, the system can perform high-frequency clock waveform verification using only low-cost ATE. The extraction of this function to the device under test eliminates the need for expensive external verification equipment while maintaining measurement precision.
Solution Approach 2:
The CUT performs self-verification of its own clock signal through the integrated verification circuit. This self-service approach allows the device to verify its own operating conditions without requiring external verification capabilities, enabling low-cost ATE to perform precise high-frequency waveform verification through the device's own resources.
Data Source
AI summary
The present invention discloses a test device for testing an integrated circuit. An embodiment of the test device includes an on-chip-clock controller (OCC), a pulse debugging circuit and a register circuit. The OCC is configured to generate an output clock according to an input clock, in which the output clock is for testing a circuitry under test (CUT) that is included in the test device. The pulse debugging circuit is configured to generate a pulse record according to a pulse number of the output clock, in which the pulse record is used to find out whether a test status dependent upon the output clock is abnormal. The register circuit is configured to store and output the pulse record according to a reliable clock.