On-Chip Clock Controller Test Circuit for ATPG Failure Diagnosis
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Solution Overview
Problem
Existing semiconductor chip testing methods face challenges in accurately diagnosing failures caused by on-chip clock controllers (OCCs) and memory elements, leading to inconsistent ATPG failure logs and potential misidentification of DUT malfunctions, due to issues like clock pulse glitches, IR drops, and pulse width sensitivity.
Innovation Solution
A system comprising an on-chip clock controller circuit, an OCC test circuit, a test output logic circuit, and a debug controller that generates and detects output clock pulses, identifies failures, and manipulates clock pulses to isolate issues, allowing for on-the-fly ATPG pattern debugging and debugging of specific flip-flops and OCCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If scan patterns are used to test DUT logic, then test coverage is improved, but false failures may occur due to OCC or memory element malfunctions
Solution Approach 1:
The patent segments the test system into separate testable units: the OCC circuit is isolated from the DUT through separate test interfaces. The OCC can be tested independently by providing test patterns to its control inputs and observing its clock pulse outputs, while the DUT can be tested independently with the OCC disabled or bypassed. This segmentation eliminates the problem where OCC failures caused false DUT failure reports.
Solution Approach 2:
The patent introduces intermediary test circuits and control logic that mediate between the test equipment and both the OCC and DUT. These intermediaries include separate scan chains for the OCC, test pattern generation circuits, and control logic that can selectively enable/disable the OCC during different test phases. This intermediary layer allows precise control and observation of clock pulse generation without affecting DUT testing integrity.
2Measurement precision
If multiple ATPG runs are performed to verify consistency, then failure diagnosis accuracy is improved, but test time increases
Solution Approach 1:
The patent performs preliminary testing of the OCC circuit separately before conducting full DUT testing. By first verifying that the OCC generates correct clock pulses through dedicated OCC test patterns and observation points, the system establishes baseline functionality. This preliminary action prevents the need for multiple repetitive ATPG runs to diagnose whether failures stem from OCC issues, thereby reducing total test time while maintaining diagnostic accuracy.
3Difficulty of detecting and measuring
If OCC test circuits are added to detect clock pulse failures, then failure detection capability is improved, but device complexity increases
Solution Approach 1:
The patent implements universal test infrastructure that serves multiple functions: the same scan chains and test pattern generation circuits are used for both OCC testing and DUT testing. The test equipment can selectively configure these universal resources to test either the OCC or the DUT by controlling enable signals and routing test patterns appropriately. This multi-functionality reduces the need for entirely separate dedicated test circuits, thereby limiting the increase in device complexity while maintaining comprehensive failure detection capability.
Data Source
AI summary
A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.