On-Cavity Photonic Integrated Circuit Backside Thermal Isolation
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Solution Overview
Problem
Existing silicon photonics micro-ring resonators in open-cavity photonic integrated circuits suffer from poor thermal isolation and inaccurate temperature measurement due to thermal cross-talk and poor thermal conductivity, which affects the stability and efficiency of wavelength division multiplexing systems.
Innovation Solution
Implement a backside etching process to create cavities through the silicon substrate, buried oxide, and cladding layers, coupled with a metallic temperature sensor placed directly above the micro-ring to enhance thermal isolation and accurate temperature measurement, and optimize bump and MRR layout to minimize footprint increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If channels are formed around the MRR to improve thermal isolation, then thermal cross-talk is reduced, but the footprint increases
Solution Approach 1:
The patent transitions from planar thermal isolation (channels around MRR) to vertical thermal isolation (backside cavity etching through substrate and cladding). By etching cavities from the backside through the silicon substrate and buried oxide layer, thermal isolation is achieved in the vertical dimension, eliminating the need for lateral channels that would increase footprint.
Solution Approach 2:
Instead of adding thermal isolation structures from the front side (channels around MRR), the patent inverts the approach by etching cavities from the backside of the device. This reverse approach allows thermal isolation to be implemented without occupying lateral space, directly addressing the footprint constraint.
2Measurement precision
If temperature sensor is placed proximate to MRR, then temperature measurement is enabled, but thermal conductivity through cladding is poor resulting in inaccurate measurement
Solution Approach 1:
The patent introduces a metallic layer as a thermal intermediary between the MRR and the temperature sensor. This metallic layer has high thermal conductivity and serves as a thermal bridge, conducting heat from the MRR to the sensor while allowing the sensor to be positioned separately. This resolves the poor thermal conductivity issue through the cladding by providing an alternative high-conductivity thermal path.
Solution Approach 2:
The patent extracts the temperature sensing function from the cladding layer and positions the sensor on the front side of the device above the MRR. By separating the sensor from the cladding and placing it in direct proximity to the MRR, the system eliminates the thermal conductivity barrier and enables accurate temperature measurement.
3Object-affected harmful factors
If backside cavity is etched through substrate and cladding, then thermal isolation is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the backside cavity etching process into distinct stages: first etching through the silicon substrate, then continuing through the buried oxide layer, and finally through the cladding layer. This segmentation allows each etching step to be optimized independently and facilitates better control over the cavity formation, reducing overall manufacturing complexity despite the multi-layer penetration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances thermal isolation and temperature control of micro-ring resonators, allowing for stable high temperatures and efficient thermal tuning without significant increase in footprint, improving the reliability and performance of wavelength division multiplexing systems.
Implementation Method 1
a metallic temperature sensor placed directly above the micro-ring to enhance thermal isolation and accurate temperature measurement
Implementation Method 2
An integrated heater is formed in the center of the micro-ring using the same P and P+ doping regions to minimize the number of necessary mask layers... The integrated heater inside the ring can heat up the ring and red-shift the resonance
Implementation Method 3
Implement a backside etching process to create cavities through the silicon substrate, buried oxide, and cladding layers, coupled with a metallic temperature sensor placed directly above the micro-ring to enhance thermal isolation and accurate temperature measurement
Data Source
AI summary
Embodiments disclosed herein include an on-cavity photonic integrated circuit (OCPIC). In an embodiment, the OCPIC comprises a laser transmitter, that comprises a row with four bumps, and a micro-ring resonator (MRR) in the row between a first bump and a second bump of the four bumps. In an embodiment, a cavity is below the MRR, where a diameter of the cavity is substantially equal to a spacing between the first bump and the second bump.