Offset-Cancellation Sensing Circuit for Non-Volatile Memory
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Solution Overview
Problem
Conventional non-volatile memory circuits face challenges in retaining memory states at reduced power levels, leading to restoration and performance degradations due to decreased sensing margin and increased process variations at near threshold voltage levels.
Innovation Solution
The implementation of an offset-cancellation sensing circuit (OCSC) that separates the sensing circuit from the latch circuit, allowing for pre-charging of differential transistors to their threshold voltages to cancel offset voltages and maintain accurate sensing of memory states without increasing transistor size, thereby maintaining performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the sensing circuit is merged with the latch circuit to reduce area, then area is reduced, but offset voltage affects sensing accuracy and requires larger transistor sizes to maintain performance
Solution Approach 1:
The patent divides the circuit into separate sensing circuit and latch circuit portions. The sensing circuit includes differential transistors for sensing memory states, while the latch circuit stores the sensed data. This segmentation allows the sensing circuit to be optimized for accuracy with pre-charged differential transistors, while the latch circuit handles storage, resolving the conflict between area reduction and sensing accuracy.
Solution Approach 2:
The patent extracts the differential transistor offset voltage issue from the overall circuit by implementing a separate sensing circuit with pre-charge capability. The pre-charge circuit charges the gates of differential transistors to their threshold voltages before sensing, effectively removing the offset voltage effect that would otherwise degrade sensing accuracy in a merged circuit configuration.
2Measurement precision
If transistor size is increased to maintain sensing margin at reduced voltage levels, then sensing accuracy is maintained, but power consumption and capacitance increase
Solution Approach 1:
The patent changes the operating parameters of the differential transistors by implementing a pre-charge mechanism that sets their gate voltages to threshold voltages before sensing operations. This parameter change allows the transistors to operate with optimal sensing margin at reduced supply voltage levels without requiring increased transistor size, thereby reducing both power consumption and capacitance while maintaining sensing accuracy.
3Use of energy by moving object
If supply voltage is reduced to conserve power in active mode, then power consumption is reduced, but sensing margin decreases and process variations increase
Solution Approach 1:
The patent implements a pre-charge phase before the sensing operation where the gates of differential transistors are charged to their threshold voltages. This preliminary action prepares the sensing circuit to operate accurately at reduced supply voltage levels by eliminating offset voltage effects, allowing the system to consume less power during active mode while maintaining adequate sensing margin despite reduced voltage and increased process variations.
Data Source
AI summary
Offset-cancellation sensing circuit (OCSC)-based Non-volatile (NV) memory circuits are disclosed. An OCSC-based NV memory circuit includes a latch circuit configured to latch a memory state from an input signal. The OCSC-based NV memory circuit also includes a sensing circuit that includes NV memory devices configured to store the latched memory state in the latch circuit for restoring the memory state in the latch circuit when recovering from a reduced power level in an idle mode. To avoid the need to increase transistor size in the sensing circuit to mitigate restoration degradation, the sensing circuit is also configured to cancel an offset voltage of a differential amplifier in the sensing circuit. In other exemplary aspects, the NV memory devices are included in the sensing circuit and coupled to the differential transistors as NMOS transistors in the differential amplifier, eliminating contribution of offset voltage from other differential PMOS transistors not included.