Octal Clock Phase Generator With Pull-Down Bias for Linear Interpolation
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Solution Overview
Problem
Conventional clock phase generators require a 2× input clock frequency to generate high-speed octal phases, increasing system complexity and cost, and struggle with phase interpolation accuracy due to phase noise and non-linearity.
Innovation Solution
A compact octal phase generator design that uses a quadrature clock phase generator to produce intermediate quad phases, which are then processed by an octal phase generator unit comprising logic gates and transistors to generate eight clock phases with 45° phase separation, incorporating a pull-down circuit and current bias circuit to minimize phase error and non-linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a quadrature clock phase generator using a frequency divider is used to generate four clock phases with 90° phase shift, then the clock phases can be generated, but a 2× input clock frequency is required which increases overall system complexity and cost
Solution Approach 1:
The patent replaces the conventional frequency divider-based quadrature clock phase generator with a new circuit architecture that uses cross-coupled logic gates and transistors to directly generate octal clock phases from a single high-speed input clock, eliminating the need for a 2× input clock frequency and reducing system complexity
Solution Approach 2:
The patent divides the clock phase generation into multiple independent units (first through eighth clock phase generation units), each generating a specific phase using cross-coupled logic gates and transistors, allowing parallel operation and reducing the complexity of any single generation path
2Productivity
If conventional clock phase generators are used to generate high-speed octal phases, then phase generation is achieved, but phase interpolation accuracy deteriorates due to phase noise and non-linearity
Solution Approach 1:
The patent incorporates pull-down circuits in each clock phase generation unit that use feedback mechanisms to actively correct phase errors and reduce non-linearity, thereby improving phase interpolation accuracy while maintaining high-speed operation
Solution Approach 2:
The patent changes the operational parameters of the clock phase generation by using cross-coupled logic gates with specific transistor configurations that optimize the phase transition characteristics, reducing phase noise and improving linearity without sacrificing generation speed
3Adaptability or versatility
If a quadrature clock phase generator is used to generate intermediate quad phases, then four clock phases with 90° phase separation are produced, but the system requires higher input clock frequency which increases cost
Solution Approach 1:
The patent creates a universal clock phase generation architecture where the same cross-coupled logic gate and transistor configuration can generate multiple phase separations (45°, 90°, 135°, etc.) by selectively enabling different clock phase generation units, eliminating the need for separate circuits for different phase requirements and reducing the input frequency requirement
Data Source
AI summary
Described herein are multi-phase clock generator embodiments for compact octal phase generation for high speed clock. A multi-phase clock generator may comprise an in-phase and quadrature (IQ) clock generator that outputs an intermediate clock signal with quad phases and an octal phase generator that generates an output clock signal comprising one or more octal phases and having a clock frequency same as an input 2-phase clock signal to the multi-phase clock generator. The multi-phase clock generator may incorporate a pull-down circuit and a current bias circuit, which may function to improve phase interpolation linearity of the octal phase generator. Histogram of phase shift error comparison shows significant improvement of a multi-phase clock generator embodiment over conventional phase interpolation.