Odd Bond Wire Power Semiconductor Current Distribution
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Solution Overview
Problem
Existing circuit arrangements for power semiconductor modules face challenges in achieving homogeneous current application to load connection areas of the same polarity using an odd number of bonding wires, which is essential for maintaining performance at operational limits.
Innovation Solution
A circuit arrangement with a substrate and conductor tracks, where a power semiconductor component is connected using an odd number of bonding wires, with the last wire having bonding feet on both load connection areas, ensuring even current distribution across the component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If an odd number of bonding wires is used to connect to load connection areas of the same polarity, then the current carrying capacity is sufficient, but homogeneous current application to both load connection areas cannot be achieved
Solution Approach 1:
The patent applies local quality by making the Nth bonding wire different from the other bonding wires. While the first N-1 bonding wires connect to only one load connection area, the Nth bonding wire connects to both load connection areas (first and second emitter connection areas). This local differentiation in connection configuration enables the odd number of bonding wires to achieve homogeneous current distribution across both load connection areas of the same polarity, resolving the contradiction between current carrying capacity and homogeneous current application.
2Device complexity
If the number of bonding wires is limited by the size of the load connection area, then the device complexity is reduced, but the current carrying capacity may be insufficient
Solution Approach 1:
The Nth bonding wire serves a dual function by connecting to both load connection areas (first and second emitter connection areas) of the same polarity. This multi-functionality allows a single bonding wire to contribute to the current carrying capacity of both connection areas simultaneously. As a result, the overall current carrying capacity is enhanced without proportionally increasing the number of bonding wires, thus addressing the contradiction between device complexity and current carrying capacity.
3Area of moving object
If power semiconductor components are reduced in lateral extent, then the area is reduced, but maintaining the same current carrying capacity becomes more difficult
Solution Approach 1:
The patent changes the connection configuration parameter by implementing an asymmetric bonding wire arrangement where the Nth bonding wire connects to both load connection areas while the other bonding wires connect to individual areas. This parameter change in the electrical connection topology allows the power semiconductor component to maintain its current carrying capacity even with reduced lateral extent, as the bonding wire configuration optimizes current distribution within the smaller area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures homogeneous current application to both load connection areas, maintaining the full performance of the power semiconductor component, even when operating at its performance limit, by distributing current evenly across the component.
Implementation Method 1
The respective power semiconductor component is electrically conductively connected to a first conductor track by means of a bond connection
Data Source
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Figure 3
AI summary
The invention relates to a circuit arrangement comprising a substrate with conductor tracks, at least one first power semiconductor device, and an associated bond connection. The first power semiconductor device has a first and a second load connection pad of the same polarity. The bond connection, in turn, has an odd number N of bond wires, wherein the first half of the N-1 bond wires extend from a first conductor track of the substrate to the first load connection pad, and the second half of the N-1 bond wires extend from this first conductor track to the second load connection pad. Furthermore, the Nth bond wire extending from the first conductor track has at least one bond foot on both the first and the second load connection pads.