Odd-Integer Clock Divider With 50% Duty Cycle at High Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional odd-integer clock dividers generate intermediate signals with frequencies higher than the input clock signal, making them unsuitable for high-speed applications, particularly in differential clock systems where precise timing and 50% duty cycle are critical.
Innovation Solution
A clock divider circuit that divides the frequency of an input clock signal by an odd integer using an edge counter, frequency multiplier, and frequency divider, ensuring the output clock signal has a 50% duty cycle without exceeding the input frequency, by counting consecutive edges and selectively combining delayed control signals to produce a balanced output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional odd-integer clock dividers are used to divide clock frequency, then the output frequency is reduced by the desired factor, but the intermediate signal frequency exceeds the input clock frequency making it unsuitable for high-speed applications
Solution Approach 1:
The frequency division process is segmented into multiple stages: a first frequency divider that divides by (N+1)/2, a second frequency divider that divides by 2, and an XOR gate that combines the intermediate signals. This segmentation allows the input clock to be divided in steps rather than in a single stage, preventing the intermediate signal frequency from exceeding the input frequency while still achieving the desired N-fold division.
Solution Approach 2:
An intermediate clock signal is introduced as a mediator in the frequency division process. This intermediate signal, generated by the first frequency divider, serves as a bridge between the high-frequency input clock and the final divided output. The intermediate signal has a frequency of fIN/(N+1)/2 which is lower than the input frequency, and it is combined with the input clock through an XOR gate to produce the final output without requiring any signal to exceed the input frequency.
2Productivity
If conventional odd-integer clock dividers are used, then frequency division is achieved, but the output duty cycle is not 50% which compromises accurate sampling in DDR systems
Solution Approach 1:
The circuit uses periodic toggling of flip-flops and systematic switching between different division paths to achieve both frequency division and duty cycle correction. The first and second frequency dividers operate periodically, and their outputs are combined through XOR logic that exploits the periodic nature of clock signals to generate a balanced 50% duty cycle output while maintaining the N-fold frequency division.
3Measurement precision
If crystal oscillators and VCOs are used to generate differential clocks, then precise timing is achieved, but the system complexity increases
Solution Approach 1:
The circuit creates copied and inverted versions of the input clock signal through the frequency dividers and XOR gate. Instead of requiring separate crystal oscillators for each clock phase, the circuit generates the necessary differential clock signals by copying and inverting the input clock through logical operations, thereby maintaining timing precision while reducing the need for additional oscillator hardware.
Data Source
AI summary
A clock divider circuit receives an input clock signal having a first frequency (f) and generates an output signal having a frequency equal to f/N, where N is an odd integer. The clock divider circuit includes an edge counter to count a number of consecutive edges of the input clock signal having a first plurality, and to assert a control signal when a threshold number (N) of consecutive edges has been counted. The clock divider circuit also includes a frequency multiplier to generate an intermediate clock signal having a frequency equal to 2f/N by doubling the frequency of the control signal based at least in part on transitions of the input clock signal, and a frequency divider to generate an output clock signal having a frequency equal to f/N by halving the frequency of the intermediate clock signal.