Odd-Integer Clock Divider Using Gated Shift Register Feedback
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Solution Overview
Problem
Existing frequency divider circuits struggle to maintain a 50/50 duty cycle when dividing a clock signal by an odd multiple, which is crucial for frequency filtering applications as it results in spectral distributions consisting only of odd harmonics.
Innovation Solution
A frequency divider circuit comprising a feedback shift register with clock gating cells and shift logic, where each second clock gating cell inverts the input clock signal, and a multiplexer generates a rotation clock signal that maintains the 50/50 duty cycle by selectively connecting gated clock signals, ensuring the output clock signal has a frequency divided by an odd integer while preserving the original duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a common clock frequency divider circuit is used to divide by an odd multiple, then the frequency division function is achieved, but the 50/50 duty cycle of the master clock frequency cannot be maintained
Solution Approach 1:
The frequency divider is segmented into multiple stages: a first frequency divider that divides the master clock by 2 to generate a 50% duty cycle intermediate clock, and a second frequency divider that divides by the odd multiple N using a chain of N D-flip-flops. This segmentation allows each stage to optimize for its specific function while maintaining overall duty cycle symmetry.
Solution Approach 2:
The invention employs feedback mechanisms where the output of the second frequency divider (dividing by odd N) is fed back to control the first frequency divider. This feedback ensures that the duty cycle symmetry is maintained by adjusting the intermediate clock based on the state of the odd multiple division, thereby preserving the 50/50 duty cycle in the final output.
2Reliability
If the duty cycle is not maintained at 50/50, then frequency filtering performance deteriorates due to presence of even harmonics
Solution Approach 1:
The circuit performs preliminary action by generating a 50% duty cycle intermediate clock signal before the odd multiple division stage. This preliminary 50% duty cycle signal serves as a clean input to the second frequency divider, ensuring that the final output maintains duty cycle symmetry and produces only odd harmonics, thereby improving frequency filtering capability.
3Device complexity
If a simple frequency divider circuit is used, then device complexity is reduced, but the ability to maintain duty cycle symmetry is lost
Solution Approach 1:
The invention introduces dynamic elements including a chain of N D-flip-flops for odd multiple division and feedback control mechanisms that dynamically adjust the intermediate clock signal. This dynamic structure allows the circuit to maintain duty cycle symmetry while achieving frequency division by odd multiples, balancing complexity with performance.
Data Source
AI summary
The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.