Odd-Integer Frequency Divider Circuit With 50/50 Duty Cycle
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Solution Overview
Problem
Existing frequency divider circuits struggle to maintain a 50/50 duty cycle when dividing a clock signal by an odd multiple, which is essential for frequency filtering applications as it results in spectral distributions consisting only of odd harmonics.
Innovation Solution
A frequency divider circuit comprising a feedback shift register with clock gating cells and a multiplexer, where each clock gating cell receives an input clock signal and generates a gated clock signal, and a multiplexer control logic that selectively connects these signals to maintain the duty cycle, using a NOR gate and latch to generate a feedback signal that ensures the duty cycle is preserved during division by odd integers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a common clock frequency is used with a divider circuit, then the clock signal can be divided down, but the original 50/50 duty cycle symmetry cannot be maintained when dividing by an odd multiple
Solution Approach 1:
The frequency divider is segmented into multiple divide stages, each handling a portion of the total division ratio. For odd integer N, the circuit uses a combination of divide-by-2 stages and a final divide-by-3 stage (or other appropriate segmentation), where each stage is designed to maintain duty cycle symmetry. This segmentation allows the overall circuit to achieve odd integer division while preserving the 50/50 duty cycle that would be lost in a simple single-stage divider.
Solution Approach 2:
The patent employs feedback mechanisms within the divider circuit to detect and correct duty cycle deviations. The feedback path monitors the output waveform characteristics and adjusts the timing or width of clock pulses to ensure the output maintains the original 50/50 duty cycle symmetry even when dividing by odd integers. This feedback control is essential for compensating for the inherent duty cycle distortion that occurs in odd-integer frequency division.
2Productivity
If the duty cycle is not maintained at 50/50, then frequency division by odd integers is achieved, but spectral purity with only odd harmonics is lost
Solution Approach 1:
The divider circuit uses dynamic timing adjustment mechanisms that adapt the pulse width and timing of internal clock signals based on the division ratio being implemented. For odd integer division, the circuit dynamically adjusts the enable signals to clock gating cells to ensure that despite the odd division ratio, the output waveform maintains the symmetrical 50/50 duty cycle required for spectral purity with only odd harmonics.
Solution Approach 2:
The patent changes key timing parameters of the clock signal throughout the division process. By carefully controlling the enable signal widths and timing relationships between different divide stages, the circuit transforms the clock signal parameters (frequency, duty cycle, phase) at each stage to ensure that the final output achieves both odd integer frequency division and maintains the 50/50 duty cycle for spectral purity.
Data Source
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AI summary
The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.