Odd-Even Bit Line Bias for Memory Programming

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Solution Overview

Problem

Electromagnetic coupling effects in non-volatile memory devices lead to undesirable widening of threshold voltage distributions during programming operations, particularly when adjacent storage elements reach a lockout condition, affecting the accuracy and reliability of data storage.

Innovation Solution

Implementing a position-based slow down measure by adjusting the bit line voltage for odd-numbered and even-numbered bit lines separately, where the programming speed of storage elements associated with odd-numbered bit lines is reduced to minimize the probability of simultaneous lockout conditions, thereby reducing capacitive coupling effects and maintaining tighter threshold voltage distributions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If programming is performed at normal speed for all bit lines, then programming productivity is maintained, but electromagnetic coupling effects cause undesirable widening of threshold voltage distributions

Engineering Contradiction:

Improvethreshold voltage distribution widthVSAvoidprogramming speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the bit lines into two groups (odd-numbered and even-numbered) and applies different programming speeds to each group. This segmentation allows the system to reduce coupling effects by staggering the programming timing between adjacent bit lines, thereby maintaining reliability while managing productivity through differentiated control strategies.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by making the programming speed position-dependent. Storage elements associated with odd-numbered bit lines are programmed at a first speed, while those associated with even-numbered bit lines are programmed at a second speed. This local differentiation targets the specific problem of capacitive coupling between adjacent bit lines while preserving overall programming functionality.

Inventive Principle:

Principle #3Local quality

2Productivity

If adjacent storage elements are programmed simultaneously, then programming efficiency is improved, but the probability of simultaneous lockout conditions increases, worsening capacitive coupling effects

Engineering Contradiction:

Improveprogramming efficiencyVSAvoidcapacitive coupling effect magnitude

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements periodic action by alternating between programming odd-numbered bit lines and even-numbered bit lines in successive programming cycles. This periodic staggering reduces the probability that adjacent storage elements will simultaneously reach lockout conditions, thereby minimizing capacitive coupling effects while maintaining reasonable programming efficiency through continued operation of both bit line groups.

Inventive Principle:

Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the probability of undesirable widening of threshold voltage distributions, enhancing the accuracy and reliability of data storage by minimizing the impact of capacitive coupling effects during programming operations.

Implementation Method 1

reducing capacitive coupling effects and maintaining tighter threshold voltage distributions

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentEP2656349B1Alternate bit line bias during programming to reduce channel-to-floating gate coupling in memory

Publication Date: 2015.06.03 SANDISK TECHNOLOGIES LLC

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AI summary

In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse. A slow down measure such as an elevated bit line voltage is applied to the storage elements of a word line which are associated with odd-numbered bit lines, but not to the storage elements associated with even-numbered bit lines. The elevated bit line voltage is applied over a range of program pulses, then stepped down to ground over one or more program pulses. The range of programming pulses over which the slow down measure is applied, can be fixed or determined adaptively. A program pulse increment can be dropped, then increased, when the bit line voltage is stepped down. Storage elements which are programmed to a highest target data state can be excluded from the slow down measure.