Odd Modulus Memory Channel Interleaving for SoC Bandwidth
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Solution Overview
Problem
Existing memory interleaving systems face complexity and cost issues when implementing odd-modulus interleaving, which is necessary for optimizing power performance and capacity in SoC devices, as it requires checking a larger number of memory address bits, increasing digital logic complexity and potentially reducing maximum speed.
Innovation Solution
A system and method for odd modulus memory channel interleaving using a dynamic random access memory (DRAM) system with a symmetric memory channel interleaver, where the memory address space is partitioned into blocks and asymmetrically configured DRAM buses provide an odd-way interleave across multiple DRAM modules, allowing for efficient distribution of DRAM traffic without excessive complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If odd-way interleaving is implemented to distribute memory traffic uniformly across memory channels, then memory bandwidth utilization is improved, but digital logic complexity increases due to requiring more address bits for channel selection
Solution Approach 1:
The patent segments the address checking function into two parts: a symmetric interleaver that handles the common portion of address bits for all channels, and asymmetric bus configurations that handle the remaining channel-specific addressing. This segmentation allows odd-way interleaving to be implemented without requiring each channel to independently handle all address bits, thereby reducing overall logic complexity while maintaining bandwidth utilization benefits
Solution Approach 2:
The patent employs asymmetric bus configurations where different memory channels have different bus widths or addressing schemes. Specifically, one channel may use a narrower bus with fewer address bits while other channels use wider buses, allowing the system to achieve odd-way interleaving without uniformly increasing the address bit width across all channels, thus reducing the complexity burden
2Productivity
If odd-way interleaving is implemented to optimize power performance and capacity in SoC devices, then memory system performance is improved, but the maximum speed of the interleaver may be reduced due to real-time address checking requirements
Solution Approach 1:
The patent performs preliminary address checking in the symmetric interleaver stage, where common address bits are processed and channel assignments are determined before data reaches the asymmetric bus stage. This preliminary action reduces the real-time checking burden on subsequent channels, allowing the system to maintain higher maximum speeds while still achieving uniform traffic distribution across all memory channels
3Productivity
If four memory channels are used to increase total bandwidth, then memory bandwidth is improved, but SoC die area increases
Solution Approach 1:
The patent designs the asymmetric bus configuration to serve multiple functions: it enables odd-way interleaving for bandwidth optimization, reduces the address bit width requirements compared to symmetric designs, and allows flexible allocation of memory capacity across channels. This multi-functionality allows the system to achieve high total bandwidth without proportionally increasing die area, as the same asymmetric infrastructure supports both bandwidth and area efficiency goals
Data Source
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AI summary
A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC comprises a first memory controller, a second memory controller, and a symmetric memory channel interleaver. The first memory controller is electrically coupled to a first DRAM module via a first memory bus. The second memory controller is electrically coupled to a second DRAM module and a third DRAM module via a second memory bus. The symmetric memory channel interleaver is configured to uniformly distribute DRAM traffic to the first memory controller and the second memory controller. The first memory controller provides a first interleaved channel to the first DRAM module via the first memory bus. The second memory controller provides a second interleaved channel to the second DRAM module via upper address bits on the second memory bus.