Odd-Modulus Memory Channel Interleaving with Asymmetric DRAM Buses
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Solution Overview
Problem
Existing memory channel interleaving technologies face complexity and cost issues when implementing odd-modulus interleaving, which limits the efficiency and bandwidth of memory systems.
Innovation Solution
A system and method for odd modulus memory channel interleaving using a dynamic random access memory (DRAM) system and a system on chip (SoC) with a symmetric memory channel interleaver, which asymmetrically configures DRAM buses to provide odd-way interleave across multiple DRAM modules, allowing for efficient distribution of memory traffic without increased complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If odd-way memory channel interleaving is implemented using conventional methods, then memory bandwidth is increased, but system complexity and cost increase significantly
Solution Approach 1:
The patent applies asymmetry by configuring memory buses with different widths for different channels. Specifically, one memory bus is configured with a first width while another memory bus is configured with a second width that is different from the first width. This asymmetric configuration enables odd-way interleaving (e.g., 3-way, 5-way) without requiring complex address checking logic, as the width differences naturally encode channel identification information.
Solution Approach 2:
The patent changes the parameter of memory bus width to enable odd-modulus interleaving. By varying the width parameter of different memory buses, the system can distinguish between different memory channels without requiring complex address bit checking. This parameter change approach transforms the interleaving mechanism from a complex logical process into a simpler physical configuration difference.
2Productivity
If more memory channels are added to increase bandwidth, then total bandwidth increases, but die area increases
Solution Approach 1:
The patent merges multiple memory channels into an odd-modulus interleaved configuration where channels are combined asymmetrically. For example, in a 3-way interleaving scenario, channels are grouped such that their address spaces are distributed across the interleaved channels, effectively combining multiple channels' bandwidth while using a manageable number of physical memory controllers and buses, thereby reducing die area compared to having separate controllers for each channel.
3Ease of manufacture
If symmetric interleaving is used for even number of channels, then implementation is simple, but odd number of channels cannot be efficiently supported
Solution Approach 1:
The patent breaks the symmetry constraint of conventional interleaving by using asymmetric memory bus configurations. Instead of requiring all memory buses to have the same width, the system deliberately uses different widths (e.g., one bus with width W1, another with width W2) to enable odd-way interleaving. This asymmetric approach provides versatility to support odd numbers of memory channels while maintaining implementation simplicity.
Data Source
AI summary
A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC comprises a first memory controller, a second memory controller, and a symmetric memory channel interleaver. The first memory controller is electrically coupled to a first DRAM module via a first memory bus. The second memory controller is electrically coupled to a second DRAM module and a third DRAM module via a second memory bus. The symmetric memory channel interleaver is configured to uniformly distribute DRAM traffic to the first memory controller and the second memory controller. The first memory controller provides a first interleaved channel to the first DRAM module via the first memory bus. The second memory controller provides a second interleaved channel to the second DRAM module via upper address bits on the second memory bus.