Odd Sum Conversion in Multiply-Accumulate Circuits

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Solution Overview

Problem

Existing analog-to-digital converters (ADCs) in multiply and accumulate circuits face challenges in accurately converting the sum of products into a digital signal, especially when the sum is odd, due to the requirement for high bit resolution and the inefficiency of using an (n−1) bit ADC.

Innovation Solution

The proposed system includes multipliers for generating products, a parity compare circuit to determine the parity of ones in the products, a conversion circuit to adjust bit values if parities differ, and an ADC coupled with a shift and add circuit to accurately convert the sum into a digital signal, even when the sum is odd.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If an (n-1) bit ADC is used to convert the sum of products, then the device complexity is reduced, but the measurement precision deteriorates when the sum is odd

Engineering Contradiction:
ImproveADC bit resolutionVSAvoidconversion accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The parity compare circuit performs preliminary detection of the sum's parity before the ADC conversion. When an odd sum is detected, the conversion circuit pre-adjusts the input signal by adding 0.5 (through bit manipulation) to ensure accurate conversion with the reduced-resolution ADC. This preliminary action prevents precision loss during the actual conversion process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The conversion circuit acts as an intermediary between the summer and the ADC. It conditionally modifies the sum signal based on parity detection, transforming odd sums into a form that can be accurately represented by the (n-1) bit ADC. This intermediary processing layer resolves the contradiction by adapting the signal to match the ADC's reduced resolution capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If the ADC directly converts the sum without parity checking, then the device complexity is reduced, but the reliability deteriorates due to conversion errors for odd sums

Engineering Contradiction:
Improveconversion circuit structureVSAvoidconversion accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system implements feedback through the parity compare circuit that continuously monitors the sum output and provides control signals to the conversion circuit. This feedback mechanism ensures that the conversion process adapts to the actual sum value, maintaining high reliability by preventing conversion errors for odd sums while keeping the overall structure relatively simple.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The conversion circuit automatically detects and corrects potential conversion errors through self-service mechanisms. The parity compare circuit independently assesses the sum parity and triggers appropriate adjustments in the conversion circuit, enabling the system to self-correct without external intervention and maintaining reliability with minimal additional complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250103293A1ODD EXCEPTION HANDLING TO ACCURATELY CONVERT A SUM OF TWO UNIFORMLY WEIGHTED 2 TO THE (n-1)th POWER BITS WITH A (n-1) BIT ADC
Publication Date: 2025.03.27 QUALCOMM INC
  • US20250103293A1 patent drawing
  • US20250103293A1 patent drawing
  • US20250103293A1 patent drawing

AI summary

A method for multiplication and accumulation includes performing multiplications on a first set of bits and a second set of bits to generate first products, and performing multiplications on a third set of bits and a fourth set of bits to generate second products. The method also includes summing the first products to generate a first sum, changing a bit value of one of the second products, and summing the second products to generate a second sum. The method further includes averaging the first sum and the second sum to obtain an average of the first sum and the second sum, converting the average of the first sum and the second sum into a digital signal, and shifting and adding a one to the digital signal.