On-Die Instrumentation Sharing DFE Samplers in Serial Receivers
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Solution Overview
Problem
Conventional on-die instrumentation (ODI) circuits for high-speed serial data links are independent and complex to integrate with decision feedback equalization (DFE) due to disturbance of the data path and reliance on speculative DFE architectures, making it difficult to implement ODI functionalities effectively.
Innovation Solution
The ODI/DFE multiplexing architecture shares sampler and reference voltage generator circuits with speculative DFE adaptation circuitry, allowing ODI to monitor real data without disturbing the data path by using the DFE adaptation path as a replica of the clock data recovery (CDR) path, and employs time multiplexing between DFE and ODI modes to simplify design and improve signal integrity and measurement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional ODI circuits are implemented independently, then ODI functionality is achieved, but circuit area increases and integration with DFE becomes complex
Solution Approach 1:
The patent merges ODI and DFE circuits by sharing the sampler and reference voltage generator, eliminating independent ODI circuitry while maintaining both functionalities through a unified architecture that reduces overall complexity
Solution Approach 2:
The shared sampler and reference voltage generator serve dual purposes: they support both DFE adaptation operations and ODI measurement functions, allowing a single circuit to perform multiple roles and reducing the need for separate dedicated components
2Measurement precision
If ODI probes data path directly, then measurement visibility is obtained, but data path disturbance occurs
Solution Approach 1:
The patent creates a copy of the data path through the DFE adaptation path, which replicates the receive signal characteristics without being the primary data path. ODI measurements are taken from this copy, providing waveform visibility while leaving the original data path undisturbed
Solution Approach 2:
The DFE adaptation path acts as an intermediary between the data path and ODI measurement circuits. It provides the measurement interface needed for ODI while isolating the data path from direct probing, thus preventing disturbance to the primary signal flow
3Reliability
If separate ODI and DFE circuits are used, then independent functionality is maintained, but circuit area increases
Solution Approach 1:
The patent combines ODI and DFE circuits into a single integrated structure where the sampler and reference voltage generator are shared resources, significantly reducing the total circuit area while maintaining both functionalities through careful architectural design
Solution Approach 2:
The shared sampler and reference voltage generator are designed to serve both ODI and DFE functions, allowing the same hardware resources to be utilized for multiple purposes and eliminating the need for separate dedicated circuits for each function
4Adaptability or versatility
If ODI uses speculative DFE architecture, then adaptation is achieved, but implementation difficulty increases
Solution Approach 1:
The patent merges ODI and speculative DFE adaptation circuits into a unified architecture where both functions share the same sampler and reference voltage generator, reducing implementation complexity while maintaining the adaptive capabilities of speculative DFE
Data Source
AI summary
One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.


