On-Die Termination Circuit Testing Through Boundary Scan
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Solution Overview
Problem
Testing on die termination (ODT) circuits in semiconductor devices is challenging due to the large number of pins involved, which complicates accurate testing and decreases accuracy, especially when testing hundreds of semiconductor memory devices simultaneously.
Innovation Solution
A semiconductor device and test system that incorporates a termination impedance control circuit, an ODT circuit, and a boundary scan circuit, which generates and stores termination impedances to output them sequentially through one pin, using a mode register set, self-control unit, and multiplexer to control transistor arrays and measure impedances accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional pin-by-pin testing method is used for ODT circuits, then each pin can be tested individually, but the number of pins required increases and testing accuracy decreases when testing hundreds of devices simultaneously
Solution Approach 1:
The patent combines multiple ODT circuit test functions into a single shared pin. Instead of requiring separate pins for each ODT circuit test, the invention allows one pin to sequentially test multiple ODT circuits by controlling the timing and sequence of tests, thereby reducing the total number of pins needed while maintaining testing accuracy
Solution Approach 2:
The patent implements periodic action by sequentially enabling and disabling different ODT circuits at different time periods during the testing process. The test controller activates one ODT circuit at a time in a time-division multiplexed manner, allowing each circuit to be tested individually through the shared pin without interference, thus maintaining measurement precision while reducing pin count
2Productivity
If multiple pins are used for simultaneous ODT testing, then parallel testing can be performed, but testing accuracy decreases due to signal interference and complexity
Solution Approach 1:
The patent uses periodic action by implementing time-division multiplexing where ODT circuits are tested sequentially rather than simultaneously. Each ODT circuit is activated and tested in a specific time slot, preventing signal interference between adjacent circuits while maintaining high testing throughput through efficient time management
Solution Approach 2:
The patent applies segmentation by dividing the testing process into discrete time segments, with each segment dedicated to testing a specific ODT circuit. The test controller segments the overall testing operation into individual circuit tests performed in sequence, allowing accurate measurement of each circuit without the interference that would occur in parallel testing
3Reliability
If ODT circuits are enabled continuously, then signal termination is always active, but testing becomes complex and accuracy decreases due to inability to isolate individual circuits
Solution Approach 1:
The patent implements dynamics by making the ODT circuit states changeable and controllable over time. Instead of having all ODT circuits permanently enabled, the system dynamically activates and deactivates specific ODT circuits based on testing requirements, allowing the termination state to adapt to the current test configuration and reducing overall testing complexity
Solution Approach 2:
The patent uses feedback mechanisms where the test controller monitors the state of each ODT circuit and adjusts the enabling/disabling of circuits based on test results and requirements. This feedback control allows the system to maintain reliable signal termination only when needed for specific tests, rather than continuously, thereby reducing testing complexity and improving accuracy
Data Source
AI summary
A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.