On-Die Termination Circuit Layout for Semiconductor Storage Devices
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Solution Overview
Problem
Current semiconductor storage devices, such as NAND flash memories, face challenges in optimizing the layout and configuration of on-die termination (ODT) circuits and drivers to minimize wiring delays and reduce chip area, while ensuring accurate timing control and preventing glitches during the switching of ODT circuits.
Innovation Solution
The proposed solution involves arranging the ODT circuit and driver adjacent to each other, with a common decoder for multiple I/O parts and allocating signal lines efficiently across multiple wiring layers to reduce wiring delays and chip area, and optionally using a delay circuit in the ODT enable signal line to synchronize the switching of ODT circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the ODT circuit and driver are arranged adjacent to each other, then wiring delays are reduced, but chip area optimization becomes more challenging
Solution Approach 1:
The ODT circuit and driver are merged into a single integrated block, eliminating the need for separate wiring between them. This combination directly reduces wiring delays while the unified structure allows for more efficient space utilization compared to separate placements.
Solution Approach 2:
The patent utilizes multi-layer wiring architecture to route signals between the ODT circuit and driver. By transitioning from planar to three-dimensional wiring布局, the design achieves short signal paths without proportionally increasing chip area, effectively resolving the space-time tradeoff.
2Area of stationary object
If a common decoder is used for multiple I/O parts, then chip area is reduced, but timing control accuracy becomes more difficult to maintain
Solution Approach 1:
The common decoder is segmented into multiple independent decoding units, each capable of generating control signals for specific I/O parts simultaneously. This segmentation allows the shared decoder structure to maintain timing precision for multiple channels while still achieving area reduction through resource sharing.
Solution Approach 2:
The decoder incorporates dynamic control mechanisms that adjust decoding timing and signal routing based on operational requirements. This dynamic capability enables a single decoder to accurately control multiple I/O parts with different timing requirements, maintaining precision while reducing area.
3Loss of time
If signal lines are allocated efficiently across multiple wiring layers, then wiring delays are reduced, but device complexity increases
Solution Approach 1:
The patent extracts and separates critical high-speed signal paths from the general wiring network, dedicating specific wiring layers exclusively to these signals. This extraction reduces interference and delays for critical paths while concentrating complexity only where necessary, rather than uniformly increasing complexity across all wiring.
Solution Approach 2:
Different wiring layers are assigned different quality characteristics based on local requirements: some layers use wide traces for high-current signals, others use shielded routes for sensitive signals, and specific layers are optimized for speed-critical paths. This localized optimization reduces overall wiring delays without requiring uniform complexity enhancement throughout the entire device.
4Measurement precision
If a delay circuit is added to the ODT enable signal line, then timing synchronization is improved, but device complexity increases
Solution Approach 1:
The delay circuit functions as an intermediary element that mediates between the ODT enable signal source and the ODT circuit trigger. By introducing this controlled delay stage, the design achieves precise timing synchronization without requiring fundamental redesign of the main ODT circuitry, thus limiting complexity increase to a localized component.
Data Source
AI summary
A semiconductor storage device in an embodiment includes a memory cell array, a pad to which data is inputted, an ODT circuit connected to the pad, an ODT driver configured to drive the ODT circuit, and a control circuit configured to supply an enable signal and a resistance value control signal to the ODT driver. The pad is arranged between the memory cell array and a first end side of the semiconductor storage device, and the ODT circuit is arranged between the pad and the first end side. The ODT driver is arranged between the ODT circuit and the first end side. An ODT control signal line configured to transmit a resistance value control signal, and an ODT enable signal line configured to transmit an enable signal are arranged between the ODT driver and the first end side.