ODT Clock Gating Circuit for Lower DRAM Idle Power
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Solution Overview
Problem
Existing ODT circuits in DRAM chips consume excessive power due to constant level switching of logic gates when no ODT command is present, leading to increased power consumption.
Innovation Solution
A control circuit with an input sampling circuit, gating generation circuit, and clock control circuit that generates a first gating signal with adjusted pulse width, ensuring the command clock signal is blocked when the ODT command is not operational, thereby preventing unnecessary current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the existing ODT circuit releases clock signals continuously even when no ODT command arrives, then the ODT circuit can respond immediately to ODT commands, but logic gates constantly switch levels consuming large current and increasing power consumption
Solution Approach 1:
The patent applies periodic action by controlling the clock signal to be released only during specific periods when ODT commands are actually present, rather than continuously. The clock control circuit generates the clock signal based on detection of ODT command presence, creating a periodic rather than continuous operation mode that reduces power consumption while maintaining response capability.
Solution Approach 2:
The patent extracts the clock signal release function from continuous operation and separates it into conditional operation based on ODT command detection. By taking out the clock signal generation and making it dependent on actual command presence, the circuit avoids unnecessary level switching and current consumption during idle periods.
2Use of energy by moving object
If the ODT circuit blocks the clock signal when no ODT command is present, then power consumption is reduced, but the response time to ODT commands may be delayed
Solution Approach 1:
The patent applies preliminary action by having the command detection circuit continuously monitor for ODT commands even when the clock signal is blocked. This preliminary detection ensures that when an ODT command arrives, the circuit is already prepared to release the clock signal immediately, eliminating any potential delay despite the blocked state.
Solution Approach 2:
The patent uses feedback through the command detection circuit that continuously monitors for ODT commands and provides feedback to the clock control circuit. This feedback mechanism ensures that the clock signal is released at the precise moment an ODT command is detected, maintaining fast response times while allowing the clock to be blocked during idle periods for power savings.
Data Source
AI summary
A control circuit includes: an input sampling circuit, configured to perform sampling processing on an initial command address signal based on a first clock signal to generate an intermediate command address signal; a gating generation circuit, configured to generate a first gating enable signal based on the intermediate command address signal and perform pulse width adjustment on the first gating enable signal based on a reset signal to generate a first gating signal; and a clock control circuit, configured to perform control processing on a second clock signal based on the first gating signal to generate a command clock signal. There is an association relationship between the level state of the first gating enable signal and the intermediate command address signal.