ODT Clock Control Circuit for Power-Down Timing Synchronization
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Solution Overview
Problem
Existing on-die termination (ODT) control circuits fail to synchronize with an external clock during power-down mode, leading to inaccurate control and timing issues, which negatively impact signal integrity and data transmission in semiconductor memory devices.
Innovation Solution
An ODT control circuit that includes a clock control circuit to select between internal and DLL clock signals based on the power mode, generating delayed clock signals to synchronize the ODT control signal with an external clock, ensuring accurate control of the ODT resistor even during power-down mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the semiconductor memory device operates in power-down mode to reduce power consumption, then power consumption is reduced, but the ODT control signal cannot be synchronized with the external clock leading to timing inaccuracies
Solution Approach 1:
The patent implements dynamic clock source selection based on power mode. During normal mode, the DLL clock is used for ODT control signal generation. During power-down mode, the system dynamically switches to using the internal clock (iCLK) as the clock source, allowing the ODT control signal to remain synchronized with the external clock edge while reducing power consumption. This dynamic adaptation resolves the contradiction between power savings and timing accuracy.
2Speed
If the swing width of signals is decreased to minimize transmission delay time, then transmission speed is improved, but external noise interference increases and signal reflection becomes critical
Solution Approach 1:
The patent dynamically changes the impedance parameter of the transmission line by controlling the ODT resistor. The ODT control signal, synchronized with the external clock edge, adjusts the termination impedance to match the characteristic impedance of the transmission line. This parameter adjustment minimizes signal reflection and noise interference while maintaining fast transmission speeds, resolving the contradiction between speed and signal integrity.
3Reliability
If on-die termination is used instead of mother board termination to improve signal integrity, then signal distortion is reduced, but the complexity of the memory device increases
Solution Approach 1:
The patent integrates the ODT control functionality into the existing memory device clocking infrastructure. The ODT control signal is generated using the same internal clock (iCLK) that is already present for other memory operations, and the control logic reuses existing components like the mode identification signal generation unit. This multi-functional approach provides signal integrity improvement without significantly increasing device complexity.
Data Source
AI summary
The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either one of the internal clock signal or the DLL clock signal according to the power mode to output a plurality of delayed clock signals; and an ODT control signal generation circuit which receives an ODT command, and controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal. According to the present invention, an ODT control signal for controlling an on-die termination resistor is synchronized with an external clock even during power-down mode, thereby more effectively controlling the ODT control signal.