ODT Clock Switching for Synchronized Termination in Power-Down
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Solution Overview
Problem
Existing on-die termination (ODT) control circuits fail to synchronize with an external clock during power-down mode, leading to inaccurate control and timing issues, which negatively impact signal integrity and data transmission in semiconductor memory devices.
Innovation Solution
An ODT control circuit that includes a clock control circuit for selecting between internal and DLL clock signals based on the power mode, and an ODT control signal generation circuit that buffers and delays these signals to generate an ODT control signal synchronized with the external clock, ensuring accurate control of the ODT resistor even during power-down mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the semiconductor memory device operates at high speed, then the operating speed increases, but signal reflection and impedance mismatching become critical
Solution Approach 1:
The patent changes the impedance parameter dynamically by controlling the on-die termination resistor to match the characteristic impedance of the signal bus. This impedance matching eliminates signal reflection and maintains signal integrity at high operating speeds.
2Loss of time
If the swing width of signals decreases to minimize delay time, then the delay time decreases, but external noise interference increases
Solution Approach 1:
The patent optimizes the signal swing width parameter to balance delay time and noise immunity. By carefully controlling the termination impedance and signal levels, the system achieves minimal delay while maintaining sufficient noise margin.
3Reliability
If the ODT control circuit uses DLL clock signals during power-down mode, then the clock synchronization is maintained, but the power consumption increases
Solution Approach 1:
The patent dynamically switches between DLL clock mode and internal clock mode based on the power mode. During active mode, DLL clocks maintain synchronization; during power-down mode, the circuit transitions to using internal clocks to reduce power consumption while maintaining necessary functionality.
4Use of energy by moving object
If the ODT control circuit switches between DLL clock and internal clock, then the power consumption is optimized, but the timing accuracy may be affected
Solution Approach 1:
The patent performs preliminary setup of internal clock timing characteristics during the design phase to ensure that when switching from DLL clock to internal clock during power-down mode, the timing accuracy requirements are met without affecting the ODT control precision.
Data Source
AI summary
The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either one of the internal clock signal or the DLL clock signal according to the power mode to output a plurality of delayed clock signals; and an ODT control signal generation circuit which receives an ODT command, and controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal. According to the present invention, an ODT control signal for controlling an on-die termination resistor is synchronized with an external clock even during power-down mode, thereby more effectively controlling the ODT control signal.