On-Die Termination Delay Control for Stable Memory ODT Latency
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in maintaining stable on-die-termination (ODT) latency due to variations in process, voltage, and temperature (PVT) conditions, as well as varying operating speeds, which can lead to malfunctions in the timing of turning on/off termination resistors.
Innovation Solution
The semiconductor memory device incorporates a delay control signal generator and a domain crossing unit that adjusts the conversion point of the termination command into the DLL clock domain signal, using test signals and a fuse option to stabilize the activation point of the termination resistors, ensuring precise impedance matching and stable ODT latency across different conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed resistor is connected externally to the memory device, then resistance matching can be achieved, but it is difficult to properly achieve resistance matching because the resistance of the termination resistor in the memory device changes due to aging, temperature variation or difference in fabrication process
Solution Approach 1:
The patent implements a dynamic termination resistor configuration where multiple termination resistors are selectively connected or disconnected based on operating conditions. The controller adjusts the termination resistance dynamically in response to temperature variations, aging effects, and fabrication process differences, transforming a static fixed resistor system into an adaptive dynamic system that maintains optimal resistance matching under varying conditions.
Solution Approach 2:
The patent changes the resistance parameter of the termination resistor by selectively connecting different resistor values in parallel or series configurations. The controller monitors operating conditions and adjusts the total termination resistance by changing which resistors are active, thereby compensating for drift caused by temperature, aging, and process variations without requiring external adjustment components.
2Reliability
If the resistance of the termination resistor is adjusted by controlling number of transistors to be turned on among a plurality of transistors connected in parallel, then resistance matching can be improved, but device complexity increases
Solution Approach 1:
The patent divides the termination resistor function into multiple discrete resistor elements that can be independently controlled. Instead of using a single complex adjustable resistor, the system segments the termination network into several fixed resistors whose combined effect is controlled by switching elements, simplifying the control logic while achieving precise resistance adjustment.
Solution Approach 2:
The patent introduces switching elements (transistors or switches) as intermediary components between the controller and the termination resistors. These intermediaries enable the controller to adjust the total termination resistance by selectively connecting different resistor elements, providing a simple and reliable mechanism for resistance adjustment without requiring complex variable resistor structures.
3Ease of operation
If ODT latency is set through mode register set, then ODT activation timing can be controlled, but timing stability deteriorates under PVT variations and varying operating speeds
Solution Approach 1:
The patent implements a feedback mechanism where the controller monitors the actual activation timing of the termination resistors and adjusts the ODT command timing accordingly. By detecting timing deviations caused by PVT variations and operating speed changes, and applying corrective adjustments, the system maintains stable ODT latency despite environmental and operational variations.
Solution Approach 2:
The patent performs preliminary timing adjustment by pre-calibrating the ODT command timing under different operating conditions. The system stores compensation values or timing offsets that are applied in advance based on detected conditions, preventing timing instability before it occurs rather than correcting it after deviation.
Data Source
AI summary
A semiconductor memory device is capable of stably securing an on-die-termination (ODT) latency in spite of PVT variations and various operating speeds. The semiconductor memory device includes a plurality of termination resistors connected to an output pad in series and parallel, a drive controller, a delay path, and a delay control signal generator. The drive controller activates/inactivates the plurality of termination resistors in response to a driving control signal. The delay path delays a termination command by a delay time corresponding to an on-die-termination (ODT) latency to output the driving control signal, wherein the termination command is converted into a delay locked loop (DLL) clock domain signal. The delay control signal generator controls a conversion point of the termination command into the DLL clock domain signal.