ODT Enable Control Circuit With Clock-Cycle Auto Disable

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Solution Overview

Problem

Current enable control circuits for On Die Termination (ODT) paths in DDR memory technologies fail to accurately control the enabled state, leading to unnecessary current waste and increased power consumption due to the inability to disable the ODT path when the ODT pin signal level does not change.

Innovation Solution

An enable control circuit comprising a counting module, a selection module, and a control module that counts past clock cycles, determines a target clock cycle count value based on configuration signals, and controls the ODT path to switch from an enabled to a disabled state when the target value is reached, ensuring the ODT path is only active during necessary resistance value changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the ODT path is kept enabled to ensure accurate resistance value switching timing, then the reliability of data transmission is improved, but power consumption increases due to unnecessary current flow when the ODT path should be disabled

Engineering Contradiction:
ImproveODT path control accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The ODT path control is made dynamic by introducing a counting circuit that tracks clock cycles and automatically transitions the ODT path from enabled to disabled state after a predetermined number of clock cycles following an ODT pin signal inversion. This dynamic control ensures the ODT path remains enabled only during the necessary period for accurate resistance value switching, then disables to reduce power consumption, thus resolving the contradiction between reliability and power consumption.

Inventive Principle:
Principle #15Dynamics

2Speed

If the ODT path is enabled continuously to maintain readiness for resistance value changes, then the speed of data transmission is improved, but current waste increases leading to higher power consumption

Engineering Contradiction:
Improvedata transmission speedVSAvoidcurrent waste
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The ODT path is activated periodically only when needed - specifically when an ODT pin signal inversion is detected and for a predetermined duration measured in clock cycles. The counting circuit implements this periodic action by enabling the ODT path upon detecting the inversion event and automatically disabling it after counting the predetermined number of clock cycles, thereby eliminating continuous current waste while maintaining transmission speed during active periods.

Inventive Principle:
Principle #19Periodic action

3Use of energy by moving object

If the ODT path is disabled to reduce power consumption, then energy efficiency is improved, but the ability to switch resistance values accurately is compromised

Engineering Contradiction:
Improvepower consumptionVSAvoidresistance value switching accuracy
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The counting circuit is pre-configured with a predetermined clock cycle count that represents the minimum time required for accurate resistance value switching. When an ODT pin signal inversion is detected, the circuit immediately enables the ODT path and starts counting, ensuring the path remains enabled for sufficient time to complete the resistance value transition before disabling. This preliminary configuration of the count value guarantees switching accuracy while minimizing unnecessary enabled time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11881254B2Enable control circuit and semiconductor memory
Publication Date: 2024.01.23 CHANGXIN MEMORY TECH INC
  • US11881254B2 patent drawing
  • US11881254B2 patent drawing
  • US11881254B2 patent drawing

AI summary

An enable control circuit and a semiconductor memory are provided. The enable control circuit includes: a counting circuit, configured to: count past clock cycles, and determine a clock cycle count value; a selection circuit, configured to determine a target clock cycle count value according to a first config signal; and a control circuit, connected to the counting circuit and the selection circuit, and configured to: control an On Die Termination (ODT) path to be in an enabled state responsive to a level state of an ODT pin signal being inverted, and start the counting circuit; and control the ODT path to switch from the enabled state to a disabled state when the clock cycle count value reaches the target clock cycle count value.