On-Die-Termination Circuit for High-Speed Memory Signal Integrity
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Solution Overview
Problem
Conventional memory systems face challenges in maintaining signal integrity at high operating frequencies, particularly in nonvolatile memory systems, which is critical for high-speed storage devices in computing and mobile communication systems.
Innovation Solution
The implementation of an on-die-termination (ODT) circuit with ODT resistors in memory chips, enabled by chip enable signals and ODT signals, allows for adaptive termination of signals, thereby reducing signal reflections and improving signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional memory systems operate at low frequencies, then signal integrity is maintained, but operating speed is limited
Solution Approach 1:
The patent implements dynamic on-die termination (ODT) that can be selectively enabled or disabled based on operational requirements. The ODT circuit adjusts its termination state dynamically during read/write operations, allowing the system to operate at high frequencies when ODT is enabled while maintaining signal integrity when ODT is disabled, thus resolving the contradiction between speed and reliability
Solution Approach 2:
The patent changes the electrical parameter (termination resistance) on-die by activating ODT circuits that present different impedance states. By modifying the termination parameter from high impedance (no ODT) to matched impedance (ODT enabled), the system can accommodate high-frequency operations without signal reflection issues, thereby improving operating frequency while maintaining signal integrity
2Device complexity
If multiple memory chips are commonly connected to shared pins, then device complexity is reduced, but signal termination control becomes difficult
Solution Approach 1:
The patent segments the ODT control for each memory chip independently while sharing the physical pins. Each memory chip has its own ODT circuit and control logic that can be independently enabled or disabled based on chip selection signals, allowing simple shared connections while maintaining independent control capability for each chip
Solution Approach 2:
Each memory chip autonomously controls its own ODT circuit based on received control signals. When a chip is selected for operation, it automatically enables its ODT circuit; when not selected, it disables ODT. This self-service approach simplifies the overall control structure while ensuring proper signal termination for active chips
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances signal integrity and reduces command overhead time, leading to improved performance and efficiency in high-speed storage devices.
Implementation Method 1
a first on-die-termination (ODT) circuit comprising a first ODT resistor... the first ODT circuit uses a first ODT resistor to terminate a signal received by at least one of the first memory chip
Data Source
AI summary
A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.