On-Die Termination Testing via Node Segmentation
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently testing on-die termination circuits, particularly in high-speed applications where signal integrity and testing time are critical, and existing parallel testing methods are not optimized for efficient on-die termination evaluation.
Innovation Solution
A memory test system is developed that includes a semiconductor memory device with specific output nodes and a coupling circuit, allowing for the generation and testing of test signals for on-die termination circuits using a small number of channels, with the ability to maintain output nodes at high impedance during the testing mode and utilize pull-down circuits to manage communication channel voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a merged-data line scheme is used for parallel testing, then test time is reduced, but it becomes difficult to efficiently test on-die termination circuits
Solution Approach 1:
The output nodes are divided into two groups: first output nodes connected to first on-die termination circuits that remain active during testing, and second output nodes connected to second on-die termination circuits that are deactivated. This segmentation allows the testing system to isolate and test specific termination circuits while maintaining others in operational state, enabling efficient on-die termination testing within the merged-data line parallel testing framework
2Reliability
If all output nodes are actively driven during testing, then signal integrity is maintained, but interference occurs between multiple driven nodes
Solution Approach 1:
The second on-die termination circuits are deactivated and extracted from the active testing scenario, allowing the first on-die termination circuits to be tested in isolation without interference from simultaneously driven nodes. This selective deactivation eliminates signal interference while maintaining signal integrity for the circuits under test
3Productivity
If multiple on-die termination circuits are tested simultaneously, then productivity is improved, but channel requirements increase
Solution Approach 1:
Multiple first output nodes are merged into a single communication channel for testing. By deactivating the second on-die termination circuits and using their associated output nodes as additional test inputs, the system can test multiple termination circuits through fewer channels, improving productivity while reducing channel requirements
Data Source
AI summary
Example embodiments relate to a memory test system having a semiconductor memory device, a coupling circuit and a tester. The semiconductor memory device may include a plurality of first output nodes and a plurality of second output nodes. The first output nodes may be connected to respective first on-die termination circuits that may not be tested, and the second output nodes may be connected to second on-die termination circuits that may be tested. The semiconductor memory device may be configured to generate test signals of the second on-die termination circuits and to provide the test signals to the second output nodes. The coupling circuit may be configured to connect the first output nodes and the second output nodes to communication channels, respectively. The tester may be configured to test a logic state of the test signals of the communication channels.