ODT Control Circuit for Shared Even-Odd Pulse Width Decoding
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Solution Overview
Problem
Conventional methods for determining ODT pulse width in semiconductor memory devices, such as DRAM, are inefficient and require a large number of logic gates, consuming significant space and power due to duplicative decoding processes for even and odd clock paths.
Innovation Solution
The ODT control circuit combines ODT off latency and CRC settings before splitting into even and odd clock paths, using compression techniques to reduce the number of logic gates required for decoding, ensuring the final RTT pulse width is even and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional decoding logic with separate even and odd clock paths is used to determine ODT pulse width, then the determination can be completed for all clock scenarios, but the number of logic gates increases leading to more space and power consumption
Solution Approach 1:
The patent merges the separate even and odd clock path decoders into a single unified decoder. The unified decoder receives a single clock signal and uses a clock enable signal to selectively generate ODT pulse widths for both even and odd clock scenarios, eliminating the need for duplicated logic gates while maintaining determination accuracy for all clock cases
Solution Approach 2:
The unified decoder is designed to perform multiple functions: it can determine ODT pulse widths for both even and odd clock signals using the same logic circuitry. By incorporating a clock enable signal that selects between different operational modes, the single decoder becomes a universal component that replaces multiple specialized decoders, reducing overall device complexity
2Reliability
If conventional decoding logic with duplication of paths is used, then all clock scenarios are covered, but power consumption increases due to the large number of logic gates
Solution Approach 1:
The patent merges the separate even and odd clock path decoders into a single unified decoder. The unified decoder receives a single clock signal and uses a clock enable signal to selectively generate ODT pulse widths for both even and odd clock scenarios, eliminating the need for duplicated logic gates while maintaining determination accuracy for all clock cases
Solution Approach 2:
The patent extracts the essential decoding function from the duplicated even and odd paths and consolidates it into a single decoder unit. By removing the redundant duplicated paths and keeping only the necessary logic gates in the unified decoder, the design reduces power consumption while preserving the ability to handle all clock scenarios through selective enabling
3Reliability
If conventional decoding logic is used, then comprehensive ODT pulse width determination is achieved, but the amount of space required increases due to more logic gates
Solution Approach 1:
The patent merges the separate even and odd clock path decoders into a single unified decoder. The unified decoder receives a single clock signal and uses a clock enable signal to selectively generate ODT pulse widths for both even and odd clock scenarios, eliminating the need for duplicated logic gates while maintaining determination accuracy for all clock cases
Solution Approach 2:
The patent segments the decoding function into modular components within the unified decoder, including separate logic paths for even and odd clock handling that are selectively activated. This segmentation allows the design to maintain comprehensive functionality while using shared resources, reducing the total space required compared to fully duplicated separate decoders
Data Source
AI summary
A memory device includes an ODT control circuit which provides an ODT pulse signal responsive to a command. The ODT control circuit compresses an ODT off latency added with a CRC bit based on a value of an ODT on latency. The compressed value of the ODT off latency added with a CRC bit is combined with the ODT on latency to generate a compressed ODT offset value. The duration of the ODT pulse signal is based on the compressed ODT offset value, a burst length, and an ODT pulse width parity. The combination of the compressed ODT offset and burst length is done along circuits of an even path or circuits of an odd path based on when the command was received. However, the compression and the generation of the ODT offset is shared between the even and odd paths.