ODT Resistance Control for Memory Channel Power Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DDR DRAM designs face significant power noise issues due to 'burst-idle' sequences that match the power delivery network's resonance frequency, which current data scrambling techniques cannot prevent.
Innovation Solution
Implementing on-die termination logic with a programmable counter and timer circuitry to introduce a tunable destructive load on the power delivery network during idle cycles, effectively muting the resonant frequency noise by controlling the assertion point and duration of the ODT resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data scrambling is implemented on DDR DRAM designs, then data security and signal integrity are improved, but power delivery noise at resonant frequency increases due to burst-idle sequences
Solution Approach 1:
The patent applies preliminary anti-action by detecting burst-idle sequences before they generate harmful resonant frequency noise, and preemptively adjusting the ODT resistance value to counteract the upcoming power delivery noise. The memory controller monitors the sequence of memory operations and modifies the termination resistance in advance to dampen resonant oscillations before they occur, thereby preventing rather than merely responding to the harmful effect.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the on-die termination (ODT) resistance value based on the detected memory operation patterns. When burst-idle sequences matching the resonant frequency are detected, the ODT resistance is modified to a different value to dampen the resonant oscillations. This dynamic parameter adjustment allows the system to adapt to varying operational conditions and eliminate the harmful resonant frequency noise while maintaining data scrambling benefits.
2Object-affected harmful factors
If ODT resistance is increased to dampen resonant frequency, then power delivery noise is reduced, but signal strength and power consumption are affected
Solution Approach 1:
The patent applies dynamics by making the ODT resistance value changeable and adaptive rather than fixed. The memory controller dynamically selects and switches between different ODT resistance values based on real-time detection of memory operation patterns and resonant frequency conditions. This dynamic adjustment allows the system to optimize noise damping only when necessary (during burst-idle sequences matching resonant frequency) while maintaining normal signal strength during regular operations, thereby resolving the contradiction between noise reduction and power consumption.
Solution Approach 2:
The patent implements parameter changes by modifying the ODT resistance value selectively based on operational conditions. Instead of maintaining a constantly high resistance to dampen noise, the system changes the resistance parameter only when burst-idle sequences are detected that would excite the resonant frequency. This selective parameter modification reduces power delivery noise while minimizing impact on signal strength and power consumption during normal memory operations.
3Reliability
If traditional termination methods are used, then signal reflections are reduced, but they cannot prevent resonant frequency oscillations caused by burst-idle sequences
Solution Approach 1:
The patent applies dynamics by transitioning from static termination resistance values to dynamic, programmable ODT resistance values that can be adjusted in real-time. The memory controller detects burst-idle sequences and programmatically changes the ODT resistance to dampen resonant frequency oscillations. This dynamic capability allows the termination method to adapt to different operational patterns and effectively suppress resonant oscillations that traditional fixed termination methods cannot prevent.
Solution Approach 2:
The patent implements parameter changes by making the termination resistance value programmable and variable. The memory controller modifies the ODT resistance parameter based on detected memory operation patterns, specifically increasing resistance during burst-idle sequences that match the resonant frequency to dampen oscillations. This parameter flexibility enables the termination mechanism to address both signal reflection control and resonant frequency suppression, overcoming the limitation of traditional fixed termination methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power delivery noise on memory channels by damping the resonant frequency oscillations, thereby improving system stability and power efficiency.
Implementation Method 1
the largest power noise events on a memory channel are now associated with 'burst-idle' sequences that approximate the power delivery network resonance frequency
Implementation Method 2
introduce a tunable destructive load on the power delivery network during idle cycles, effectively muting the resonant frequency noise
Data Source
AI summary
A device, computer system, and method are disclosed. In one embodiment, the device includes a memory buffer driver circuit that can drive signals on a memory channel at a given voltage level. The voltage at the voltage level is supplied to the memory buffer driver circuit from a rail of a power delivery network. The voltage level exhibits a repeatable fluctuation cycle at a resonant frequency of the power delivery network. The device also includes an on-die termination logic circuit that asserts a first termination resistance on the memory channel after the memory channel enters an idle state but before the voltage level reaches a peak of the repeatable fluctuation cycle. The on-die termination logic circuit then deasserts the first termination resistance on the memory channel at a later point in time.