On-Die Termination Timing Shift Before DLL Delay Line
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Solution Overview
Problem
Existing memory systems face high power consumption during on-die termination (ODT) operations due to the need for clock signals to pass through delay circuits, which is inefficient and increases energy usage.
Innovation Solution
Locating the ODT shifter before the cloned DLL delay line allows the clock signal to bypass the DLL delay line during ODT operations, reducing power consumption by blocking the clock signal from entering the DLL delay line during ODT commands and only passing it through during read or write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal passes through the DLL delay line during ODT operations, then the ODT timing can be synchronized with the DLL domain, but power consumption increases due to unnecessary clock signal processing
Solution Approach 1:
The ODT shifter is positioned before the DLL delay line to perform the shifting operation in advance, allowing the clock signal to bypass the power-consuming DLL delay line during ODT operations while still achieving proper timing synchronization
Solution Approach 2:
The ODT shifter is extracted from the DLL delay line path and placed independently before it, allowing the clock signal to be separated from the delay line during ODT operations, thus eliminating unnecessary power consumption while maintaining timing accuracy
2Reliability
If the ODT shifter is located after the cloned DLL delay line, then the ODT information can be properly synchronized to the DLL domain, but the clock signal must pass through the delay line increasing power consumption by up to 3 mA
Solution Approach 1:
The ODT shifter performs the timing adjustment operation before the clock signal enters the DLL delay line, allowing the signal to be pre-synchronized and then bypass the power-consuming delay line during ODT operations
Solution Approach 2:
The ODT shifter acts as an intermediary component that prepares the ODT information in advance, allowing the main clock signal path to bypass the DLL delay line during ODT operations while still achieving proper synchronization
Data Source
AI summary
Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.