On-Die Termination Timing Control in Semiconductor Memory
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Solution Overview
Problem
High-speed semiconductor memory devices face challenges in adjusting on-die termination (ODT) timing to comply with specifications, particularly at higher clock frequencies, due to fluctuations in ODT operation characteristics, making it difficult to maintain optimal data transmission speeds.
Innovation Solution
A semiconductor memory device with latency control units, trimming control units, and termination circuits that produce and adjust ODT driving signals to control the connection and disconnection of termination resistances at specific impedance nodes, allowing for precise timing adjustments to meet ODT timing parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to achieve higher data transmission speed, then the data I/O speed improves, but the ODT timing parameter compliance becomes more difficult to achieve
Solution Approach 1:
The patent implements dynamic ODT timing adjustment by providing multiple ODT timing modes (first ODT timing mode and second ODT timing mode) that can be selectively activated based on the operating conditions. The ODT timing adjustment unit dynamically switches between different timing configurations to optimize both high-speed operation and specification compliance at different clock frequencies.
Solution Approach 2:
The patent changes the ODT timing parameters by adjusting the activation and inactivation times of the termination resistance. The ODT timing adjustment unit modifies these timing parameters based on the selected ODT timing mode, allowing the system to adapt to different clock frequencies while maintaining specification compliance.
2Speed
If the termination resistance is connected earlier to improve data transmission readiness, then the data I/O speed improves, but the ODT operation time increases causing timing parameter violations
Solution Approach 1:
The patent uses dynamic control of the ODT operation duration by providing different ODT timing modes. In the first ODT timing mode, the termination resistance is activated earlier with a longer operation time, while in the second ODT timing mode, the activation is delayed with a shorter operation time. This dynamic adjustment allows optimization of both speed and timing parameter compliance.
Solution Approach 2:
The ODT operation is controlled in periodic cycles corresponding to clock cycles, with the termination resistance being activated and deactivated at specific periods. The ODT timing adjustment unit controls the duration and timing of these periodic ODT operations to balance speed requirements with timing parameter constraints.
3Ease of operation
If the ODT operation is activated early to prepare for data reception, then the data transmission readiness improves, but the power consumption increases
Solution Approach 1:
The patent implements dynamic power management for the ODT operation by selectively activating different ODT timing modes based on the operational requirements. The ODT timing adjustment unit controls when the termination resistance is activated, allowing the system to balance between being ready for immediate data reception and minimizing power consumption during idle periods.
4Speed
If the termination resistance is disposed inside the semiconductor memory device to improve data transmission speed, then the data I/O speed improves, but the device complexity increases
Solution Approach 1:
The patent combines the ODT timing adjustment functionality with the existing memory device architecture by integrating the ODT timing adjustment unit and termination resistance within the memory device. This merging approach allows the system to achieve high-speed data transmission while keeping the overall device structure relatively compact and manageable.
Data Source
AI summary
A semiconductor memory device is effectively able to adjust operation time for on-die termination (ODT). The semiconductor memory device includes a latency control unit, a control signal generating unit, a trimming control unit, and a termination circuit. The latency control unit produces an ODT driving enable signal by delaying an ODT operation signal from an external circuit during a predetermined latency. The control signal generating unit produces control signals to control a change of waveform of the ODT driving enable signal. The trimming control unit changes the waveform of the ODT driving enable signal in response to the control signals, thereby outputting a ODT driving signal. The termination circuit connects a termination resistance to an impedance adjusting node in response to the ODT driving signal.