On-Die Termination Timing Shift for Lower-Power DLL Operation
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Solution Overview
Problem
Existing memory systems face high power consumption during on-die termination (ODT) operations due to the need for clock signals to pass through delay lines, which is inefficient and increases energy usage.
Innovation Solution
Locating the ODT shifter before the cloned DLL delay line allows the clock signal to bypass the DLL delay line during ODT operations, reducing power consumption by blocking the clock signal from entering the DLL delay line during ODT commands and only passing it through during read or write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal passes through the DLL delay line during ODT operations, then the ODT timing can be synchronized with the DLL domain, but power consumption increases due to unnecessary current usage
Solution Approach 1:
The patent segments the clock signal path by creating separate paths for ODT operations versus read/write operations. The ODT shifter is positioned before the delay line and can operate independently, allowing the clock signal to bypass the power-consuming DLL delay line during ODT operations while still achieving proper timing synchronization through the dedicated ODT timing path.
Solution Approach 2:
The patent implements dynamic control of the clock signal path using control logic that determines whether to route the clock signal through the DLL delay line based on the operation type. During ODT operations, the clock signal is routed directly to the ODT shifter, bypassing the delay line. During read/write operations, the clock signal passes through the delay line. This dynamic routing optimizes power consumption while maintaining correct timing for different operation types.
2Reliability
If the ODT shifter is located after the cloned DLL delay line, then the ODT information is properly synchronized to the DLL domain, but the clock signal cannot be blocked during ODT operations, leading to higher power consumption
Solution Approach 1:
The patent applies preliminary action by performing the ODT shifting operation before the signal enters the DLL delay line. The ODT shifter is repositioned to operate on the ODT information in the CLKS domain before it needs to be synchronized to the DLL domain. This allows the timing alignment to be established early in the signal path, enabling the subsequent blocking of the clock signal during ODT operations without compromising synchronization accuracy.
Solution Approach 2:
The patent introduces an intermediary control mechanism that manages the clock signal routing between the ODT shifter and the DLL delay line. The control logic acts as an intermediary, detecting when an ODT operation is active and blocking the clock signal from entering the delay line, thereby preventing unnecessary power consumption while maintaining proper ODT timing through the dedicated ODT timing path.
3Reliability
If the clock signal is continuously passed through the DLL delay line, then the DLL domain synchronization is maintained, but unnecessary current is consumed during ODT operations
Solution Approach 1:
The patent implements periodic action by controlling the clock signal to pass through the DLL delay line only when necessary (during read/write operations) and blocking it during ODT operations. The control logic periodically enables or disables the clock signal path based on the current operation type, reducing energy loss during ODT operations while maintaining DLL domain synchronization when needed.
Solution Approach 2:
The patent applies local quality by creating different signal path characteristics for different operational contexts. The clock signal path is modified locally at the control logic stage to provide different routing options: one path through the DLL delay line for read/write operations requiring synchronization, and another direct path for ODT operations where the delay line should be bypassed to reduce power consumption.
Data Source
AI summary
Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.