On-Die Termination Timing Control for Memory Signal Integrity
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Solution Overview
Problem
Existing signal transmitting and receiving apparatuses and memory devices face performance degradation due to the simultaneous enablement and disablement of on-die termination circuits, which leads to preamble and postamble time issues during signal transmission and reception.
Innovation Solution
The apparatus includes independent control over the enable and disable timing of first and second on-die termination circuits connected to different pins, allowing the second circuit to be enabled only after the first, thereby preventing performance degradation caused by simultaneous termination circuit operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If on-die termination circuits are simultaneously enabled and disabled, then signal transmission can occur, but performance degradation occurs due to preamble and postamble time issues
Solution Approach 1:
The patent divides the termination control into separate enable and disable timing for different termination circuits (e.g., DQ termination and RDQS termination). This segmentation allows independent optimization of each circuit's activation and deactivation times, preventing the performance degradation caused by simultaneous enablement/disablement of all termination circuits.
2Reliability
If multiple on-die termination circuits are controlled independently with different enable/disable timing, then performance degradation is avoided, but control complexity increases
Solution Approach 1:
The patent implements dynamic control of termination circuits by allowing different enable and disable timing for each termination circuit based on operational requirements. The termination control circuit dynamically adjusts the timing parameters (e.g., enabling DQ termination before RDQS termination, and disabling them in a staggered sequence) to optimize signal integrity without requiring overly complex static control logic.
Data Source
AI summary
A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.