ODUCn Mapping Using Partition Memories to Reduce FIFO Complexity

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Solution Overview

Problem

Existing ODUk mapping implementation solutions are inadequate for ODUCn mapping, leading to issues with logic scale, implementation complexity, and universality, as they require large numbers of FIFO caches and data selectors, resulting in resource wastage and high implementation costs.

Innovation Solution

A method and apparatus for ODUCn mapping that involves caching low-order ODUj data into partition memories, generating and encoding values Cm and ∑Cnd, and using a modulation algorithm to read and select time slot data, packaging it into ODUC1 frames with dynamic partition sizes and efficient data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If existing ODUk mapping implementation solutions are adopted for ODUCn mapping, then mapping functionality can be achieved, but the number of FIFO caches and processing complexity increases significantly

Engineering Contradiction:
Improvemapping functionalityVSAvoidnumber of FIFO caches
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a single set of n partition memories that can serve multiple ODUCn frames simultaneously. Instead of requiring separate FIFO caches for each time slot and ODUCn frame, the system uses one universal memory structure that handles all mapping operations, reducing the total number of caches from m×n to just n.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functions of multiple FIFO caches into a single set of partition memories. By combining the time-slot-specific caching functions into one unified memory structure with n partitions, the system eliminates redundant cache structures while maintaining the ability to handle multiple time slots and ODUCn frames efficiently.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If existing ODUk mapping solutions are used for ODUCn, then mapping can be implemented, but implementation complexity and resource consumption increase

Engineering Contradiction:
Improvemapping implementationVSAvoidimplementation complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent uses a universal mapping approach where a single set of n partition memories handles all ODUCn frame mappings. This multi-functional design eliminates the need for separate caching mechanisms for each time slot, significantly simplifying the implementation while maintaining full mapping functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the fundamental parameter of memory organization from time-slot-specific FIFO caches to a unified partition-based memory structure. This parameter change transforms the mapping implementation from a complex multi-cache system to a simplified single-memory-system, reducing implementation difficulty.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If multiple FIFO caches are used for each time slot in ODUCn mapping, then data mapping can be performed, but resource wastage occurs

Engineering Contradiction:
Improvedata mapping capabilityVSAvoidresource consumption
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements a universal memory structure where n partition memories serve multiple purposes across different time slots and ODUCn frames. This multi-functional approach allows the same memory resources to be reused, eliminating resource wastage while maintaining full data mapping capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

By merging the caching functions into a single unified memory structure, the patent eliminates redundant memory allocations. The n partition memories collectively replace what would traditionally require m×n separate FIFO caches, significantly reducing resource consumption.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3528442B1Method, device, computer storage medium for mapping optical channel data unit frames
Publication Date: 2020.12.30 SANECHIPS TECH CO LTD
  • EP3528442B1 patent drawingFigure 1~2
  • EP3528442B1 patent drawingFigure 3
  • EP3528442B1 patent drawingFigure 4

AI summary

The embodiment of the present invention discloses a mapping method of optical channel data unit Cn (ODUCn), which includes: caching low-order ODUj data into n partition memories according to a port time slot configured for each low-order ODUj data; generating a value Cm of the number of m-bit data entities and a value ∑Cnd of the number of accumulated remaining bits which cannot form the m-bit data entities according to a rate of low-order ODUj data stream, and encoding the values of Cm and ∑Cnd; generating a read signal of cached data by utilizing a modulation algorithm and according to the value of Cm, reading low-order ODUj data cached in the partition memories, and selecting required time slot data from the read data; packaging the selected time slot data and the encoded values of Cm and ∑Cnd into n ODUC1 frames according to a generated ODUC control signal. The embodiment of the present invention also discloses a mapping apparatus of ODUCn and a computer storage medium.