Reversal-Amenable ODVS Codes for Bus Signal Integrity

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Solution Overview

Problem

Existing communication systems face challenges in maintaining reliable and efficient data transfer over bus-reversed channels, leading to signal degradation and increased receiver complexity due to impedance anomalies and impractical physical reordering of signals.

Innovation Solution

The development of reversal-amenable Orthogonal Differential Vector Signaling (ODVS) codes, which allow for efficient detection and permutation of signals using digital logic, reducing the need for complex analog circuitry and minimizing signal degradation by transforming bus-reversed signals into valid codewords through judicious permutation of the generating matrix columns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If physical reordering of signals is performed to correct bus reversal, then signal integrity is improved, but device complexity and implementation difficulty increase significantly

Engineering Contradiction:
Improvesignal integrityVSAvoidreceiver complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces physical reordering of signal wires (mechanical approach) with digital logic processing (electronic approach). Instead of physically rearranging bus lines through complex routing and switching hardware, the system uses digital permutation logic to reorder signal values after detection, thereby correcting bus reversal effects while maintaining simpler physical infrastructure

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an intermediary digital processing stage between signal detection and final data interpretation. This intermediary layer performs permutation operations on detected signal values, acting as a mediator that corrects bus reversal effects without requiring direct physical reconfiguration of the signal path, thus decoupling the correction function from the physical hardware complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If analog circuitry is used for signal reordering, then signal degradation is minimized, but device complexity and power consumption increase

Engineering Contradiction:
Improvesignal qualityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent substitutes analog signal processing with digital logic operations. Instead of using complex analog circuitry to physically reorder signals (which would consume significant power and introduce analog degradation), the system detects signals analogously but then uses digital permutation logic to correct bus reversal, achieving signal quality improvement with lower power consumption

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If impedance anomalies are corrected through physical routing changes, then signal integrity is improved, but ease of manufacture and implementation decrease

Engineering Contradiction:
Improvesignal integrityVSAvoidimplementation ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces complex physical routing changes (which would be difficult to manufacture and implement) with digital logic-based signal permutation. This allows the same signal integrity improvement to be achieved through software or digital logic configuration rather than physical hardware reconfiguration, significantly easing manufacturing and implementation

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10404394B2Bus reversible orthogonal differential vector signaling codes
Publication Date: 2019.09.03 KANDOU LABS SA
  • US10404394B2 patent drawing
  • US10404394B2 patent drawing
  • US10404394B2 patent drawing

AI summary

Properties and the construction method of Orthogonal Differential Vector Signaling Codes are disclosed which are tolerant of order-reversal, as may occur when physical routing of communications channel wires causes the bus signal order to be reversed. Operation using the described codes with such bus-reversed signals can avoid complete logical or physical re-ordering of received signals or other significant duplication of receiver resources.