ODVS Codes Embed Clock in DRAM Data
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Solution Overview
Problem
Current DRAM interfaces face challenges in increasing data transfer rates without degrading signal integrity, particularly due to misalignment of DRAM data and strobe signals, and the need for multi-phased processing which complicates clock extraction and transition detection.
Innovation Solution
The implementation of orthogonal differential vector signaling (ODVS) codes that embed a clock signal within the data transmission, using multi-input comparators and specific codeword structures like 5b6w, 8b9w, and ENRZ codes to enhance signal integrity and support higher data transfer rates while maintaining compatibility with existing CMOS and DRAM processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM data transfer rate is increased, then productivity is improved, but signal integrity deteriorates due to misalignment between data and strobe signals
Solution Approach 1:
The patent merges the clock signal with the data transmission by embedding clock information within the data itself using ODVS codes. This eliminates the separate strobe signal path that causes misalignment, allowing high-speed data transfer while maintaining synchronization and signal integrity through the integrated encoding scheme.
Solution Approach 2:
The patent introduces multi-input comparators as intermediary devices that detect transitions in the ODVS encoded signals. These comparators serve as mediators between the transmitted signal and the sampling clock, enabling accurate timing recovery without requiring a separate external strobe signal, thus maintaining signal integrity at high transfer rates.
2Reliability
If multi-phased processing is used for clock extraction, then clock synchronization is achieved, but device complexity increases
Solution Approach 1:
The ODVS encoding scheme is self-synchronizing, automatically providing timing information within the data stream itself. The embedded clock information in the transition patterns allows the receiver to self-adjust and synchronize without requiring complex external clock recovery circuits or multi-phased processing, thereby reducing device complexity while maintaining synchronization.
3Reliability
If orthogonal differential vector signaling codes with embedded clock are used, then signal integrity is improved, but device complexity increases due to encoding requirements
Solution Approach 1:
The patent changes the parameter representation by using transition-based encoding in ODVS codes rather than traditional voltage-level encoding. This parameter transformation embeds clock information in the transition patterns themselves, improving signal integrity and timing synchronization while the encoding complexity is managed through systematic code design and lookup tables that can be implemented in standard CMOS processes.
Data Source
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AI summary
Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.