OFDM Time Deinterleaver Architecture With Reduced Memory Addressing
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Solution Overview
Problem
In OFDM-based ISDB-T communication systems, the deinterleaver design requires large memory and complex counter implementations, leading to increased power consumption and area, which is undesirable.
Innovation Solution
The proposed solution involves a deinterleaver apparatus with a practical OFDM symbol counter of 25-30 bits, a divider for calculating intra-buffer offset, and lookup tables for obtaining delay buffer sizes and buffer base addresses, implemented using ROM or dynamic arithmetic calculations, to reduce the complexity and area of the deinterleaver design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RAM based deinterleaver design is used, then deinterleaving function is achieved, but device area and power consumption increase due to large number of memory pointers and counters
Solution Approach 1:
The patent extracts and removes the large number of memory pointers and counters from the RAM-based deinterleaver design. By eliminating these unnecessary components, the design achieves significant area reduction while maintaining the deinterleaving function through a simplified architecture that uses only essential memory structures and control logic.
Solution Approach 2:
The patent applies local quality by optimizing specific parts of the deinterleaver architecture. Instead of uniformly using RAM with full pointer and counter implementations throughout, the design selectively applies memory structures only where needed, with simplified control logic in other regions, thereby reducing overall area while preserving functional requirements.
2Ease of operation
If large number of counters are implemented, then memory addressing is achieved, but device area increases due to flip-flop implementation
Solution Approach 1:
The patent removes the large number of counters that would be implemented as flip-flops. By extracting this functionality and replacing it with a simplified control mechanism, the design maintains adequate memory addressing capability while eliminating the area overhead associated with numerous counter circuits.
Solution Approach 2:
The patent implements a universal control approach where a single control logic unit handles memory addressing for all memory structures. This multi-functional controller replaces the need for dedicated counters for each memory block, significantly reducing the total number of flip-flops required while maintaining comprehensive addressing capability.
3Reliability
If conventional deinterleaver design is used, then deinterleaving functionality is provided, but chip area is large
Solution Approach 1:
The patent segments the deinterleaver design into distinct functional blocks: input buffer, memory structures for different transmission layers, and output buffer. This segmentation allows each component to be optimized independently, eliminating redundant elements and reducing overall chip area while maintaining complete deinterleaving functionality for multiple layers.
Solution Approach 2:
The patent merges control functions into a unified control logic that manages all memory structures and data flow. By combining what would traditionally be separate control units for each memory block into a single intelligent controller, the design reduces the total number of logic elements and achieves significant area savings.
Data Source
AI summary
A method and apparatus for de-interleaving interleaved data in a deinterleaver memory in an Orthogonal Frequency Division Multiplexing (OFDM) based Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver. In different embodiments, the apparatus comprises of a OFDM symbol counter along with a divider or a buffer pointer RAM with circular pointer logic, a first lookup table to obtain delay buffer size and interleaving lengths for a given OFDM transmission layer, and a second lookup table to obtain buffer base address and interleaving lengths for a given OFDM transmission layer.