OFDM Deinterleaver PLL Control for Data Stream Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital video broadcasting (DVB) receivers face challenges in minimizing jitter in data streams due to dynamic guard intervals and echo effects in OFDM signals, leading to increased complexity and hardware requirements in FEC circuitry.
Innovation Solution
A deinterleaver system with a digital phase lock loop (PLL) and asynchronous read/write operations is implemented to control jitter, using memory to store OFDM symbols and adjust reading rates based on channel conditions, thereby reducing output jitter to less than half a carrier clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If byte rate smoothing is provided at the rear end of FEC circuitry, then output jitter is reduced, but hardware complexity and chip real estate increase due to additional memory requirements
Solution Approach 1:
The patent combines the deinterleaving function with jitter control by using the same memory structure for both purposes. The memory that stores OFDM symbols for deinterleaving also serves as the buffer for jitter control, eliminating the need for separate additional memory at the backend of FEC circuitry.
Solution Approach 2:
The deinterleaver memory is designed to perform multiple functions: it stores incoming OFDM symbols for deinterleaving operations and simultaneously acts as a buffer to absorb jitter variations. This multi-functional approach reduces overall hardware requirements while maintaining both deinterleaving and jitter control capabilities.
2Reliability
If static data stream smoothing is implemented for worst case scenario, then jitter is controlled, but processing efficiency decreases due to constant gap absorption capability
Solution Approach 1:
The patent implements dynamic jitter control where the reading rate from memory is continuously adjusted based on actual channel conditions. The digital PLL dynamically modifies the read clock frequency to match the actual arrival rate of OFDM symbols, rather than using a fixed conservative rate. This allows the system to adapt to varying guard interval durations and channel conditions, improving processing efficiency while maintaining jitter control.
3Reliability
If additional memory is provided to absorb demodulation bursts, then output jitter is reduced, but chip real estate consumption increases
Solution Approach 1:
The patent merges the burst absorption function with the existing deinterleaver memory. The same memory array that stores OFDM symbols for deinterleaving operations also absorbs the bursts caused by varying guard intervals and synchronization jumps. By properly timing the read operations using digital PLL control, the memory efficiently handles both deinterleaving and jitter absorption without requiring additional chip real estate.
Data Source
AI summary
In one embodiment, the present invention includes a deinterleaver having an input interface to receive orthogonal frequency division multiplexing (OFDM) symbols from a demodulator, a memory coupled to the input interface to store the OFDM symbols, an output interface coupled to the memory to receive the OFDM symbols stored in the memory, and a digital phase lock loop (PLL) to control and adjust a reading rate of data from the memory responsive to dynamic and static channel conditions.