OFDM De-Interleaving Address Generation for DVB-T2 Sub-Carrier Separation
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Solution Overview
Problem
Current DVB-T and DVB-H systems face challenges in error correction due to correlated fading in terrestrial broadcast channels, which affects the integrity of data communication, particularly in the 2k, 8k, and 4k modes, as existing interleaving schemes do not effectively separate data symbols across sub-carrier signals.
Innovation Solution
A data processing apparatus with an interleaver memory and address generator that includes a linear feedback shift register and permutation circuit, which generates pseudo-random addresses to de-interleave data symbols from OFDM sub-carriers, using an odd interleaving process to reduce the likelihood of successive data bits being mapped onto the same sub-carrier, and incorporating an offset or sequence of permutation codes to improve error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interleaving schemes are used in DVB-T/DVB-H systems, then data symbols are mapped onto sub-carrier signals, but successive data bits remain likely to be mapped onto the same sub-carrier due to correlated fading, worsening error correction performance
Solution Approach 1:
The patent applies dynamics by making the interleaving pattern variable rather than fixed. The address generator uses a linear feedback shift register that changes the mapping pattern dynamically, ensuring that successive data bits are separated across different sub-carriers in each OFDM symbol, thereby combating correlated fading effects
Solution Approach 2:
The patent changes the parameter of address generation by introducing a linear feedback shift register with specific tap positions (e.g., 10th and 7th stages for 2k mode, 12th and 9th stages for 8k mode) that generate pseudo-random addresses. This parameter change transforms the static interleaving into a dynamic process that adapts to different modes and improves symbol separation
2Reliability
If a linear feedback shift register with permutation circuit is used to generate addresses, then data symbols are better separated across sub-carriers, but the device complexity increases
Solution Approach 1:
The patent introduces an intermediary element - the linear feedback shift register with permutation circuit - that acts as a mediator between the data symbols and sub-carrier mapping. This intermediary generates pseudo-random addresses that achieve better symbol separation without requiring complex external control systems
Solution Approach 2:
The address generator is self-service in that it automatically generates the required addresses using internal feedback from its own shift register stages. The system uses its own output fed back through XOR operations to generate new addresses, eliminating the need for external address lookup tables or complex control logic
3Manufacturing precision
If mode-specific address generation is implemented for 2k, 8k, and 4k modes, then optimal interleaving is achieved for each mode, but the adaptability to different modes requires multiple configurations
Solution Approach 1:
The patent achieves universality by designing a single address generator structure that can operate in multiple modes (2k, 8k, 4k) by simply changing the tap positions of the linear feedback shift register. The same basic circuit architecture serves all modes, eliminating the need for completely separate address generation systems for each mode
Data Source
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AI summary
A data processing apparatus maps symbols received from a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols into an output symbol stream. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the sub-carrier signals into the output symbols stream. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has nine register stages and the permutation code forms, with an additional bit, a ten bit address. The address generator includes an offset generator operable to add an offset to the formed ten bit address, thereby providing an improvement in de-interleaving the data symbols for a 1K operating mode of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2). This is because there is a reduced likelihood that successive data bits which are close in order in an input data stream are mapped onto the same sub-carrier of an OFDM symbol.