OFDM De-Interleaving Address Generation for DVB-T2 0.5K Mode
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Solution Overview
Problem
Existing OFDM systems, such as DVB-T and DVB-H, face challenges in error correction due to correlated fading in terrestrial broadcast channels, which can be mitigated by effectively interleaving data symbols across sub-carrier signals, but current methods are not optimal, especially for the 0.5K operating mode of DVB-T2.
Innovation Solution
A data processing apparatus with an address generator that includes a linear feedback shift register and a permutation circuit, which generates pseudo-random bit sequences and changes permutation codes for each OFDM symbol, adding an offset to addresses to de-interleave data symbols efficiently, thereby reducing the likelihood of successive data bits being mapped onto the same sub-carrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data symbols are mapped onto sub-carrier signals using conventional interleaving methods, then error correction can be performed, but successive data bits may be mapped onto the same sub-carrier due to correlated fading, reducing error correction efficiency
Solution Approach 1:
The patent applies dynamics by making the interleaving pattern variable rather than fixed. Different interleaving patterns are used for different OFDM symbols, and within each symbol, different code rates can have different interleaving arrangements. This dynamic adaptation ensures that successive data bits are separated across different sub-carriers even when channel conditions vary, preventing correlated fading from affecting adjacent bits simultaneously and thereby improving error correction efficiency
Solution Approach 2:
The patent changes the parameter of interleaving pattern to resolve the contradiction. By varying the interleaving pattern based on code rate and OFDM symbol index, the system ensures that data bits are distributed across sub-carriers in a way that avoids concentrated mapping. This parameter change adapts the interleaving behavior to different operating conditions, preventing the harmful effect of correlated fading while maintaining reliable error correction
2Manufacturing precision
If interleaver memory size is increased to improve de-interleaving performance, then data symbol mapping accuracy improves, but device complexity and memory requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the interleaving process into multiple stages or passes. Instead of requiring a large memory to hold all data symbols for complete de-interleaving, the system processes data in segments across different OFDM symbols with different interleaving patterns. This segmented approach achieves accurate data symbol mapping while reducing the memory footprint of the interleaver by processing smaller chunks of data at each stage
Solution Approach 2:
The patent uses periodic action by repeating the interleaving process across multiple OFDM symbols with varying patterns. Rather than requiring all data to be stored simultaneously in large memory, the system periodically processes data symbols through the interleaver with different patterns for each symbol. This periodic processing achieves accurate mapping while keeping memory requirements bounded by the size needed for a single symbol's worth of data
Data Source
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AI summary
A data processing apparatus maps symbols received from a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols into an output symbol stream. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the sub-carrier signals into the output symbol stream. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eight register stages and the permutation code forms, with an additional bit, a nine bit address. The address generator includes an offset generator operable to add an offset to the formed nine bit address, thereby providing an improvement in de-interleaving the data symbols for a 0.5K operating mode of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2). This is because there is a reduced likelihood that successive data bits which are close in order in an input data stream are mapped onto the same sub-carrier of an OFDM symbol.