OFDM Interleaver Address Generation for Multi-Mode DVB
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Solution Overview
Problem
The existing Digital Video Broadcasting (DVB) standards, such as DVB-T and DVB-H, face challenges in efficiently interleaving data symbols onto Orthogonal Frequency Division Multiplexed (OFDM) sub-carrier signals, particularly in lower modes like 0.5 k and 1 k modes, which affects error correction coding performance due to correlated fading in terrestrial broadcast channels.
Innovation Solution
A data processing apparatus with a linear feedback shift register and permutation circuit generates addresses for interleaving data symbols onto OFDM sub-carriers, optimizing the interleaving process by using a specific generator polynomial and permutation order, allowing flexible implementation across various modes, including 0.5 k, 1 k, 2 k, 4 k, 8 k, 16 k, and 32 k modes, and enabling efficient error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing DVB standards use conventional interleaving methods for 2k, 8k modes, then the implementation is standardized, but the error correction performance deteriorates in lower modes (0.5k, 1k) due to correlated fading
Solution Approach 1:
The patent develops a universal interleaver design that can operate across multiple DVB modes (0.5k, 1k, 2k, 8k, 16k, 32k) by configuring the interleaver depth and generator polynomial according to the specific mode. This allows a single apparatus to provide optimized error correction performance for all modes, particularly improving lower modes while maintaining compatibility with higher modes through parameter adjustment.
Solution Approach 2:
The patent changes key parameters of the interleaver including the generator polynomial, interleaver depth, and permutation order to optimize performance for different modes. By adjusting these parameters, the system achieves improved error correction performance in lower modes (0.5k, 1k) while maintaining functionality across the full range of DVB modes.
2Reliability
If the interleaver depth is increased to improve error correction in lower modes, then the reliability improves, but the device complexity increases
Solution Approach 1:
The patent optimizes the interleaver depth parameter for each mode to achieve the necessary error correction performance without excessive complexity. For lower modes (0.5k, 1k), the interleaver depth is increased to combat correlated fading, while for higher modes (2k, 8k, 16k, 32k), the depth is adjusted to an appropriate level, avoiding unnecessary complexity while maintaining performance.
3Reliability
If a mode-specific interleaver is designed for each DVB mode, then the error correction performance is optimized for that mode, but the manufacturing cost and implementation complexity increase
Solution Approach 1:
The patent creates a universal interleaver apparatus that can be implemented once and configured for multiple DVB modes (0.5k, 1k, 2k, 8k, 16k, 32k). This single implementation provides mode-specific optimization through parameter configuration rather than requiring separate hardware designs, thereby reducing manufacturing cost and implementation complexity while maintaining optimized error correction performance for each mode.
Data Source
AI summary
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.


