OFDM Interleaver Addressing for Variable Sub-Carrier Mapping

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Solution Overview

Problem

Existing OFDM systems face challenges in efficiently adapting to varying numbers of sub-carriers per symbol, leading to increased memory requirements and complexity, which hinders flexible data communication and increases costs.

Innovation Solution

A data processing apparatus with a controller, address generator, and interleaver memory that operates in odd-even interleaving mode, allowing for dynamic mapping of input symbols onto sub-carrier signals, minimizing memory usage by validating addresses for each OFDM symbol and using a single interleaver memory size equal to the maximum number of sub-carriers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of sub-carriers per OFDM symbol is made variable to accommodate different communication modes, then adaptability is improved, but memory requirements and device complexity increase

Engineering Contradiction:
Improveadaptability to varying sub-carrier countsVSAvoidmemory requirements and system complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic adaptability by enabling the OFDM system to vary the number of sub-carriers per symbol based on communication mode requirements (e.g., 2k, 8k modes). The controller dynamically adjusts the interleaving parameters and address generation to match the current sub-carrier count, allowing the system to adapt to different communication standards and conditions without requiring fixed memory allocation for maximum capacity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes key parameters including the interleaver memory size, address generation algorithm, and mapping configuration based on the detected communication mode. When operating in a mode with fewer sub-carriers (e.g., 2k mode), the system reduces the interleaver memory allocation and adjusts the address generation to match the reduced sub-carrier count, thereby maintaining adaptability while minimizing memory requirements and device complexity.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a single interleaver memory size equal to maximum sub-carriers is used, then device complexity is reduced, but memory usage efficiency decreases when fewer sub-carriers are available

Engineering Contradiction:
Improveinterleaver memory management complexityVSAvoidmemory usage efficiency
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent employs a universal interleaver memory design where a single memory structure serves multiple communication modes (2k, 8k, and intermediate modes). The memory is configured with a size equal to the maximum sub-carrier count, but the system achieves mode-specific optimization through dynamic address generation and selective memory region utilization. This universal approach simplifies hardware design while maintaining efficiency through software-controlled parameter adjustment.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically adjusts memory addressing and allocation based on the active communication mode. When operating in modes with fewer sub-carriers, the address generation algorithm selectively addresses only the required portion of the interleaver memory, effectively reducing memory usage without requiring physical memory reconfiguration. This dynamic addressing ensures efficient memory utilization across varying sub-carrier counts while maintaining a fixed memory structure.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If address validation is performed for each OFDM symbol to accommodate varying sub-carrier counts, then adaptability is improved, but processing time and complexity increase

Engineering Contradiction:
Improveflexibility in accommodating varying sub-carrier countsVSAvoidprocessing time for address validation
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs preliminary configuration of address generation parameters and interleaving patterns based on the detected communication mode before actual data transmission begins. The controller pre-configures the address generator with mode-specific parameters (such as sub-carrier count, interleaver size, and mapping patterns), so that during operation, address validation proceeds efficiently using pre-established rules rather than requiring extensive runtime validation for each symbol.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the controller continuously monitors the communication mode and sub-carrier count, and dynamically adjusts address generation parameters in real-time. This feedback loop ensures that address validation is optimized for the current operating conditions, reducing processing overhead by adapting validation rules to match the active communication mode rather than using fixed, conservative validation for all modes.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP2129068B1Data processing apparatus and method
Publication Date: 2019.07.03 SATURN LICENSING LLC
  • EP2129068B1 patent drawingFigure 1
  • EP2129068B1 patent drawingFigure 2
  • EP2129068B1 patent drawingFigure 3

AI summary

A data processing apparatus is operable to map input data symbols to be communicated onto sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The number of sub-carrier signals the available from each of the OFDM symbols being variable between OFDM symbols and the input data symbols include first sets of data symbols and second sets of input data symbols. The data processing apparatus includes a controller, an address generator and an interleaver memory. The controller is operable, when operating in accordance with an even interleaving process to read out a first set of the input data symbols from the interleaver memory on to the sub-carrier signals of an even OFDM symbol using read addresses generated by the address generator, and to write in a second set of the input data symbols into the interleaver memory using the addresses generated by the address generator. The controller is operable in accordance with an odd interleaving process, to read out a first set of input data symbols from the interleaver memory on to the sub-carrier signals of an odd OFDM symbol using read addresses determined in accordance with a sequential order of the first set of input data symbols, and to write in a second set of the input data symbols into the interleaver memory at write addresses determined in accordance with the sequential order of the first group of input data symbols. The controller is operable to determine before reading out the first input data symbols from the interleaver memory, whether the read address is valid for a previous OFDM symbol, and to determine before writing the second input data symbols into the interleaver memory, whether the write address is valid for a current OFDM symbol. As such, the interleaver memory size can be minimised to an amount which corresponds to a maximum number of sub-carriers, which are available for any of the OFDM symbols. Application can be found with Cable 22, which can provide substantially four thousand carriers.