OFDM Symbol Interleaver Addressing for DVB-T2 1K Mode
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Solution Overview
Problem
The existing DVB-T standard lacks a symbol interleaver for the 1k mode, which is required for more severe mobile communication environments, and existing solutions struggle to optimize error correction coding performance due to correlated fading in terrestrial broadcast channels.
Innovation Solution
A data processing apparatus that maps data symbols from OFDM sub-carrier signals into an output stream using a de-interleaver and address generator, featuring a linear feedback shift register and permutation circuit to generate pseudo-random addresses, optimizing the interleaving of symbols across sub-carriers for improved error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symbol interleaver is added to the 1k mode to improve error correction performance, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the generator polynomial and permutation order parameters of the address generator to create different interleaving patterns optimized for the 1k mode. Specifically, it uses a generator polynomial of degree 9 with specific tap positions and a permutation code that maps shift register outputs to address bits in a non-sequential manner, achieving effective symbol interleaving while maintaining a relatively simple hardware structure.
Solution Approach 2:
The address generator design achieves universality by being capable of generating addresses for multiple OFDM modes (1k, 2k, 4k, 8k, 16k) through parameter reconfiguration. The same basic architecture with a 9-stage shift register and permutation circuit can be adapted to different sub-carrier configurations by changing the generator polynomial coefficients and permutation mapping, making the interleaver structure versatile across different DVB-T2 modes.
2Adaptability or versatility
If the number of sub-carriers is increased to 1024 for 1k mode, then the adaptability is improved, but the difficulty of detecting and measuring increases
Solution Approach 1:
The patent replaces complex address generation algorithms with a hardware-based linear feedback shift register system. Instead of using software-based random number generation or complex arithmetic operations to generate addresses for 1024 sub-carriers, the invention uses a deterministic pseudo-random sequence generated by an LFSR with specific feedback taps, which can be implemented efficiently in hardware with simple XOR operations and register stages.
Solution Approach 2:
The address generation process is segmented into distinct functional blocks: a 9-stage shift register for generating the base sequence, a permutation circuit for reordering the bits according to a predefined permutation code, and an address assembly unit that combines these to form the final 10-bit addresses. This segmentation makes the complex task of generating addresses for 1024 sub-carriers manageable and implementable through modular hardware components.
Data Source
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AI summary
A data processor maps data symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream. The data processing apparatus comprises a interleaver arranged to read-into an interleaver memory the predetermined number of data symbols from the OFDM sub-carrier signals, and to read-out of the interleaver memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals. An address generator is arranged to generate the set of addresses, an address being generated for each of the received data symbols to indicate the OFDM sub-carrier signal from which the received data symbol is to be mapped into the output symbol stream. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register is Riʹ8=Ri-1ʹ0⊕Ri-1ʹ4, and a permutation code is provided for permuting the order of the content of the register stages. The permutation code has been established by simulation analysis to optimise communication performance via typical radio channels. As such, a 1K operating is provided with an interleaver, which can interleave data symbols onto approximately one thousand sub-carriers of OFDM symbols for an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestria12 (DVB-T2) or DVB-Cable2 (DVB-C2).