OFDM Symbol Interleaver Addressing for DVB-T2 16k Mode
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Solution Overview
Problem
The existing DVB-T and DVB-H standards lack an efficient symbol interleaver for the 16k mode, which is necessary for providing a more sparse deployment of DVB transmitters in a single frequency network, requiring improved error correction coding performance due to correlated fading in terrestrial broadcast channels.
Innovation Solution
A data processing apparatus with a linear feedback shift register and permutation circuit that generates pseudo-random bit sequences and addresses for mapping input symbols onto OFDM sub-carrier signals, utilizing a specific generator polynomial and permutation order to achieve optimal interleaving for the 16k mode, allowing flexible implementation across different modes by changing the taps and permutation orders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symbol interleaver is provided for the 16k mode to improve error correction coding performance, then the reliability of data communication is improved, but the device complexity increases due to the need for additional address generation circuits and memory structures
Solution Approach 1:
The address generator is designed to be mode-flexible, capable of operating in 2k, 4k, 8k, and 16k modes by changing software control parameters rather than hardware configuration. The same basic circuit structure (LFSR with permutation circuit) serves multiple modes, reducing overall system complexity while maintaining reliability across different transmission requirements
Solution Approach 2:
The invention changes the operational parameters of the address generator (register stage count, feedback polynomial, permutation order) to adapt to different modes. For 16k mode specifically, it uses 13 register stages with polynomial x^13 + x^12 + x^8 + x^5 + 1 and a specific permutation order, allowing the system to achieve improved reliability for sparse transmitter deployment without redesigning the entire interleaver structure
2Adaptability or versatility
If the number of sub-carrier signals is increased to approximately sixteen thousand for sparser transmitter deployment, then the coverage area and network flexibility are improved, but the manufacturing precision requirements increase due to the need for accurate address generation and symbol mapping
Solution Approach 1:
The address generator employs a linear feedback shift register with a carefully selected feedback polynomial (x^13 + x^12 + x^8 + x^5 + 1) that ensures uniform distribution of addresses across all 16384 sub-carriers. The feedback mechanism provides mathematical guarantee of address uniqueness and uniformity, achieving the required precision for sparse transmitter deployment without requiring complex calibration or adjustment mechanisms
Solution Approach 2:
The permutation circuit pre-arranges the address bits according to a predetermined permutation order before the addresses are used for symbol mapping. This preliminary bit reordering ensures that the addresses are uniformly distributed across the 16k sub-carriers from the start, eliminating the need for runtime adjustments or corrections and maintaining high precision throughout operation
3Productivity
If a linear feedback shift register with thirteen register stages is used to generate pseudo-random bit sequences for 16k mode, then the productivity of address generation is improved, but the loss of information may occur if the sequence length is not optimal
Solution Approach 1:
The invention selects specific parameters for the LFSR system: 13 register stages, feedback polynomial x^13 + x^12 + x^8 + x^5 + 1, and a specific permutation order. These parameters were chosen to achieve a maximum sequence length of 2^13 - 1 = 8191 bits, which is optimal for generating unique addresses for 16384 sub-carriers when combined with the permutation circuit and counter. This ensures complete coverage without repetition or information loss while maintaining high generation speed
Solution Approach 2:
The address generation process is segmented into three independent but coordinated components: the LFSR generates a pseudo-random bit sequence, the permutation circuit reorders the bits according to a fixed permutation, and a counter provides additional addressing information. This segmentation allows each component to be optimized independently - the LFSR for speed, the permutation for distribution uniformity, and the counter for complete address space coverage - achieving both high productivity and information completeness
Data Source
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AI summary
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register of Riʹ12=Ri-1ʹ0⊕Ri-1ʹ1⊕Ri-1ʹ4⊕Ri-1ʹ5⊕Ri-1ʹ9⊕Ri-1ʹ11 is provided with a permutation order which has been established by simulation analysis to optimise communication performance via typical radio channels, of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2).