OFDM Symbol Interleaver Addressing for DVB-T2 1K Mode

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Solution Overview

Problem

The existing DVB-T and DVB-H standards lack an efficient symbol interleaver for the 1k mode, which is necessary for OFDM communications in harsh environments with high time variations, requiring a solution to optimize error correction coding schemes and accommodate multiple frequency networks.

Innovation Solution

A data processing apparatus with a linear feedback shift register and permutation circuit generates addresses for interleaving input data symbols onto OFDM sub-carrier signals, using a specific generator polynomial and permutation code to create a 1k mode symbol interleaver, allowing flexible implementation across different modes by changing the generator polynomial and permutation order.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a symbol interleaver is implemented for the 1k mode using existing DVB-T and DVB-H standards, then the communication can support standard modes (2k, 8k, 4k), but the 1k mode specific optimization for harsh environments with high time variations is not achieved

Engineering Contradiction:
Improveerror correction performanceVSAvoidmode flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent modifies the generator polynomial parameters of the linear feedback shift register to create optimized interleaving patterns specifically for the 1k mode. By changing the polynomial coefficients and register configuration, the system achieves enhanced error correction performance tailored to harsh environments with high time variations, while maintaining compatibility with the overall DVB-T2 framework that supports multiple modes.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a dedicated 1k mode symbol interleaver is designed, then error correction performance in harsh environments is optimized, but the device complexity increases compared to using existing standard modes

Engineering Contradiction:
Improvecommunication integrityVSAvoidinterleaver configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent designs a universal address generator architecture that can operate with different generator polynomials and permutation codes to support multiple modes (1k, 2k, 4k, 8k, 16k) within a single device. The interleaver structure remains consistent across modes, with only the polynomial parameters and permutation sequences needing adjustment, thereby reducing overall device complexity while maintaining optimized performance for the 1k mode in harsh environments.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If existing address generators from DVB-T and DVB-H standards are used, then implementation is cost-effective and simple, but they lack the specific optimization needed for 1k mode in harsh environments with high time variations

Engineering Contradiction:
Improveimplementation costVSAvoiderror correction coding performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the address generation function into distinct components: a linear feedback shift register with configurable generator polynomial, a permutation circuit with mode-specific permutation codes, and an address output unit. This modular segmentation allows the system to use simple, cost-effective hardware structures while achieving optimized 1k mode performance through configurable polynomial parameters and permutation sequences tailored to harsh environment requirements.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP2056472B1Data processing apparatus and method
Publication Date: 2009.12.09 SONY GROUP CORP
  • EP2056472B1 patent drawingFigure 1
  • EP2056472B1 patent drawingFigure 2
  • EP2056472B1 patent drawingFigure 3

AI summary

A data processor maps input data symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register is Riʹ8=Ri-1ʹ0⊕Ri-1ʹ4, and a permutation code is provided for permuting the order of the content of the register stages. The permutation code has been established by simulation analysis to optimise communication performance via typical radio channels. As such, a 1K operating is provided with an interleaver, which can interleave data symbols onto approximately one thousand sub-carriers of OFDM symbols for an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestria12 (DVB-T2) or DVB-Cable2.