OFDM Symbol Interleaver Addressing for DVB-T2 32k Mode
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Solution Overview
Problem
The existing DVB-T and DVB-H standards lack an efficient symbol interleaver for the 32k mode, which is necessary for providing a more sparse deployment of DVB transmitters in a single frequency network, and for optimizing error correction coding schemes in OFDM systems, especially in mobile applications where channel estimation needs frequent updates.
Innovation Solution
A data processing apparatus with a de-interleaver and address generator that maps and de-maps symbols from OFDM sub-carrier signals using a linear feedback shift register and permutation circuit, optimized for the 32k mode with a specific generator polynomial and permutation order, allowing flexible operation across different modes by adjusting the maximum valid address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symbol interleaver is provided for the 32k mode, then data integrity and error correction performance are improved, but device complexity increases due to the need for additional address generation circuitry and memory structures
Solution Approach 1:
The address generator is designed to support multiple OFDM modes (2k, 8k, and 32k) using a unified architecture. The same LFSR and permutation circuit structure is reused across different modes by adjusting parameters such as the generator polynomial and permutation order, rather than implementing separate interleavers for each mode. This reduces overall device complexity while maintaining reliability across all modes.
Solution Approach 2:
The invention changes key parameters of the address generator to adapt to different OFDM modes. Specifically, the generator polynomial of the LFSR and the permutation order are modified based on the required mode (2k, 8k, or 32k). This allows a single device structure to achieve mode-specific optimization without requiring separate hardware implementations, thereby improving reliability for 32k mode while controlling device complexity.
2Adaptability or versatility
If the number of sub-carriers is increased to 32k, then the sparse deployment of DVB transmitters is improved, but the processing speed and channel estimation update frequency deteriorate
Solution Approach 1:
The invention implements dynamic parameter adjustment within the address generator to optimize performance for different operational scenarios. The system can dynamically switch between different generator polynomials and permutation orders depending on the OFDM mode being used, allowing fast channel estimation updates in mobile applications while maintaining the benefits of 32k sub-carriers for sparse transmitter deployment.
3Productivity
If a linear feedback shift register with specific polynomial is used, then the pseudo-random sequence generation for address mapping is optimized, but the device complexity increases due to additional register stages and permutation circuits
Solution Approach 1:
The address generator uses a universal LFSR structure with configurable parameters that can be adjusted to optimize performance for different OFDM modes. The same basic circuit architecture (LFSR + permutation circuit) is used across all modes, with only the generator polynomial and permutation order changing. This maintains productivity through efficient pseudo-random sequence generation while controlling device complexity through parameterization rather than structural multiplication.
4Manufacturing precision
If the permutation circuit is configured with specific permutation order, then the symbol mapping accuracy is improved, but the ease of manufacture deteriorates due to customized circuit configuration
Solution Approach 1:
The invention achieves different symbol mapping accuracies for various OFDM modes by changing the permutation order parameter rather than redesigning the permutation circuit structure. The same circuit topology is manufactured once, and the permutation order is configured through programming or initialization based on the required mode (2k, 8k, or 32k). This maintains manufacturing precision while significantly improving ease of manufacture compared to custom-designed circuits for each mode.
Data Source
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AI summary
A data processing apparatus maps data symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output data stream. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register of Riʹ13=Ri-1ʹ0⊕Ri-1ʹ1⊕Ri-1ʹ2⊕Ri-1ʹ12 is provided with a permutation order which has been established by simulation analysis to optimise communication performance via typical radio channels, of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2).